ECE 559 MOS VLSI Design Project

Fall 2024 – Sections 005, 007 and FNY (Group Projects)

Goal: In this project, you will design an 8-bit Wallace Tree Multiplier, including its schematic,

layout, simulation, functionality verification and timing/energy/area analysis.

Wallace Tree Multiplier Overview:

The Wallace Tree Multiplier is a hardware implementation technique in digital circuit design

for high-speed multiplication. It was introduced by Chris Wallace in 1964. This multiplier

approach reduces the computation time by reducing the number of sequential adding stages.

The multiplier generally contains three components: partial product generator, partial

product reduction, and final adder.

The partial product generator component will be responsible for generating 8x8-bit partial

products via ANDing bits of the multiplicand with each bit of the multiplier input (the 8x8

dot parallelogram in the first picture of figure 1).

The partial product reduction part will reduce the partial products into two partial sums for

the final addition. It utilizes both half and full adder to reduce the partial products into partial

sums. After each reduction pass, the total number of partial result rows will be reduced by 1.

For instance, there are 2 reduction passes from the top picture of figure 1 to the second picture.

The first pass operates on row 0-2 of the partial products, and the second pass operates on

row 3-5 of the partial products. When both reductions are done, the total number of partial

result rows is reduced from 8 to 6.

The final adder component will add up the two remaining partial results to produce the

multiplication result, representing by the last picture with two rows in figure 1.

Figure 1: 8-bit Wallace Tree algorithm1

For this project, you will implement the partial product generator, implement full and half

adder blocks, determine the adder array for each reduction pass, and implement a final

adder of your choice (ripple-carry adder, carry-select adder, etc.).

Project Specifications and Guidelines:

Multiplier Design:

• N = 8 (for the 8-bit multiplier).

• Input rise/fall time: 50ps.

• Output load: 2fF.

Layout Design:

• Layout must be DRC-clean and LVS-clean.

• Extract parasitics from the layout and report post-layout energy and propagation

delay values under worst case.

Evaluation Metrics:

• Pass functionality check.

• Worst-case propagation delay: ≤ 3ns.

• Energy consumption (considering the same input vectors as the delay analysis): ≤

1000fJ.

• Minimize the area while adhering to the above performance constraints.

Worst-Case Scenario:

• Identify the worst-case input(s) for delay and report the corresponding metrics. You

will need to justify your worst-case input(s).

Bonus: Design and analyse a 8-bit Multiply-Accumulate (MAC) unit using your

implementation of Wallace Tree multiplier with your choice of a adder. The layout

implementation will be required. Demonstrate its functionality and evaluate its delay, energy

consumption and area. Successful implementation of the MAC unit with earn extra credit.

Reference:

1. h\ps://en.wikipedia.org/wiki/Wallace_tree