2023 EXAMINATIONS
PART II (Third)
ENGINEERING
(1.5 hours)
ENGR332: Integrated Circuit Engineering
Answer all TWO questions.
See Appendix at the end of the paper
2
A1 Answer ALL parts (a) – (d)
(a) Given the words WL(i) (I = 1, 2, 3) with 4 bits:
WL (1) 0011
WL (2) 1110
WL (3) 1001
(i) Draw the dot diagram representing the MOS NAND ROM with the given
words.
(2 marks)
(ii) Draw the schematics of the MOS NAND ROM to store the given words.
(6 marks)
(b) You wish to increase the yield of your fabrication process for integrated
circuits from 30% to 50%. Assume your circuit has 3 cm
2
die area and the
wafer diameter is 18 inches. (Assume the parameter = 3 and ).
(i) Provide the solution to increase the fabrication yield from 30% to 50%.
(3 marks)
(ii) Calculate the total number of dies the wafer contains.
(2 marks)
(iii) Calculate the number of good dies and the number of bad dies in case
of 30% yield and 50% yield.
(2 marks)
(c) Given the logical function 퐹 = (퐴+퐵)∙퐶∙(퐷+퐸)
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
, derive the circuit of the
CMOS gate that performs the logical function F.
(5 marks)
PLEASE TURN OVER
3
(d) Given the C
2
MOS circuit in Figure A1-1, demonstrate with the aid of diagrams
that the circuit is insensitive to (1-1) clock overlap and specify the condition of
validity of this property.
Figure A1-1
(5 marks)
PLEASE TURN OVER
M
1
D
Q
M
3
CLK
M
4
M
2
CLK
V
DD
C
L
1
X
C
L
2
Master Stage
M
5
M
7
CLK
CLK
M
8
M
6
V
DD
Slave Stage
4
A2 Answer ALL parts (a) – (c)
(a) CMOS integrated circuit technology has substantially progressed in the past
year achieving chips with billions of transistors. Power consumption is an
important parameter of integrated circuits.
(i) Describe the main components of power dissipation in a CMOS circuit
and write down an appropriate equation for power dissipation.
(3 marks)
(ii) Discuss how power consumption can be reduced in a CMOS circuit.
(3 marks)
(iii) Explain why power consumption in a CMOS chip is not proportional to
the number of transistors per chip.
(4 marks)
(b) The propagation delay of a CMOS NAND is dependent on the data input
pattern.
(i) Draw the schematic and the RC equivalent model for a 2 inputs NAND
CMOS, including the internal capacitance of the pull-down stack.
(2 marks)
(ii) Compute the different propagation delays for a 2 inputs NAND CMOS
as a function of the different data input patterns, ignoring the effect of
the internal capacitance, highlighting the pattern that produces the
shorter delay and the longer delay.
Assume R
p
= 15 k, R
n
= 5 k, C
L
= 2 fF.
(4 marks)
(iii) For which data input pattern must the contribution of the internal
capacitance be included for a reliable computation of the propagation
delay?
(2 marks)
PLEASE TURN OVER
5
(c) A typical synchronous system is shown in Figure A2-1.
Figure A2-1
The following parameters are set:
f Clock frequency 1 GHz
t
c-q
Clock-to-Q Propagation Delay 100 ps
t
cdreg
Clock-to-Q Contamination Delay 55 ps
t
su
Setup Time 50 ps
t
hold
Hold time 60 ps
(i) Compute the maximum logic propagation delay and minimum logic
contamination delay to satisfy the maximum time delay constraint and
race condition.
(4 marks)
(ii) In case of clock skew = 100 ps, are the maximum time delay
constraint and race condition computed in (i) still valid?
If not, compute the new the maximum logic propagation delay and
minimum logic contamination delay to satisfy the maximum time
delay constraint and race condition.
(3 marks)
PAPER ENDS
6
APPENDIX – Useful formulae
Equations for question A1 b.
dieaera is the die area
푑푖푒푠 푝푒푟 푤푎푓푒푟=
휋 ∙(푤푎푓푒푟푑푖푎푚푒푡푒푟/2)
2
푑푖푒 푎푟푒푎
−
휋 ∙푤푎푓푒푟푑푖푎푚푒푡푒푟
√
2∙푑푖푒푎푟푒푎
푑푖푒 푦푖푒푙푑=( 1+
푑푒푓푒푐푡푠 푝푒푟 푢푛푖푡 푎푟푒푎∙ 푑푖푒푎푟푒푎
훼
)
−훼
