ENT672 Coursework 2 Roberto Quaglia – Kauser Chaudhry
Coursework 2
Design and simulation of a circuit with MIM capacitors
Cardiff University – School of Engineering – Centre for High Frequency Engineering
ENT672 Coursework 2 Roberto Quaglia – Kauser Chaudhry
Coursework
GaN transistor processes have the advantage of being able to operate at relatively high bias voltage, improving the power density when designing power amplifiers.
However, this put stress on other components, in particular capacitors, since they will be subjected to higher electric field than in other processes, such as GaAs-based.
The NP15 process you are using can operate transistors at 20 V.
However, the manufacturer has notified us that the reliability of MIM capacitors decreases dramatically when a voltage higher than 12 V DC is applied to a capacitor.
But we still need a shunt capacitance of 0.5 pF for our design.
The objective is to find a circuit that provides a 0.5 pF shunt capacitance at 30 GHz; the overall circuit must be able to sustain 20 V DC with each MIM capacitor not exceeding 12 V of applied DC voltage.
These are the steps you should cover:
- Think of a method of obtaining an equivalent capacitance using capacitors where each capacitor has a lower DC voltage applied.
- Perform circuit simulation using the PDK NP15 including the via-hole and MIM models. Tune the values to obtain 0.5 pF of equivalent capacitance.
- Generate a layout taking care of layers and components overlap, and perform EM simulations
- Compare the EM simulations with circuit simulations.
- Adjust the layout to achieve 0.5 pF equivalent at 30 GHz.
For each of these points, when creating your short report, show me the important schematics, layouts and plots, and when you are making design choices explain me why you made such a choice.
FILES TO SUBMIT: a pdf file of the report; the archived project (to archive a project, go to the main ADS page, click on File→Archive Workspace, select the workspace to archive and decide where to save the file). Submit it on Learning Central in Assignments.
DEADLINE: Deadline November, 13th 2022, 23:59pm
Cardiff University – School of Engineering – Centre for High Frequency Engineering
