Lab Assignment 1

EE5518 – AY2023/2024 Sem1 Submission Deadline: 16th October’23 11:59AM

Lab experience 1: Getting started with Cadence Virtuoso via Interconnect Modelling and Simulation.

Consider a 2-core processor with 2 dedicated GPUs and 2 DSP cores in 45nm operating at 1V and max frequency of 200MHz. The path to each block from the RESET PIN is shown in Fig. 1 along with the corresponding global/intermediate (solid-black/dotted-blue) interconnect lengths. The interconnects are assumed to be drawn with minimum widths allowed by the technology node. Using an ideal voltage source VRST and a 3kΩ resistor at the RESET PIN, reset signal is triggered at t = 0, synchronous to rising edge of clock. The input capacitance of the reset buffer in each block is shown via the dashed arrows in Fig. 1.