ENT672 Coursework 1 Roberto Quaglia – Aleksander Bogusz
Coursework 1
Transistor amplifier design and simulation using Win PDK
Cardiff University – School of Engineering – Centre for High Frequency Engineering
ENT672 Coursework 1 Roberto Quaglia – Aleksander Bogusz
Coursework
The objective is to simulate the single-tone and two-tone response of a FET common-source amplifier that works at 900 MHz, based on the 8x100um transistor of the NP15 Win process.
These are the steps you should cover:
- Simulate the DCIV characteristics of the FET (ID vs. VDS for several VGS, ID vs. VGS for several VDS) (remember multiple swept variables?). Limit the drain voltage to 20-22 V to avoid model problems. This is a depletion mode FET, what should be the sweep on the gate?
??
- Select a bias point in the active (saturation) region of the transistor
- Create a harmonic balance simulation that includes transistor, bias tees (see L2) to provide
the needed gate and drain voltage, and a single tone voltage source with internal 50 Ohm resistance. The load resistance can be between 10 and 100 Ohm.
- Evaluate the small signal gain of the amplifier in the selected bias point and tune the bias point and the load resistance to achieve a small signal voltage gain of at least 21 dB.
- Sweep the input voltage to determine the maximum voltage and output power your amplifier can deliver {remember that for phasors the power corresponding to voltage V1 and current I1.i is given by 0.5*real(V1*conj(I1.i))}. But remember that we are interested in the fundamental!
- Show and discuss a plot of gain vs. input power.
- Set up a 2-tone harmonic balance simulation for your amplifier and apply two tones with same
amplitude and phase at 890 MHz and 910 MHz, both at small input drive level and near the 2
Cardiff University – School of Engineering – Centre for High Frequency Engineering
ENT672 Coursework 1 Roberto Quaglia – Aleksander Bogusz
maximum allowed. Observe the response, especially the output spectrum and time domain signal, and critically comment on it.
For each of these points, when creating your short report, show me the important schematics and plots, and when you are making design choices (for example, the bias-point) explain me why you made such a choice.
The format of the report is up to you; but please no more than 4-5 pages. Do not waste pages on introductions on transistors, amplifiers, etc. but still put 2-3 lines explaining why in your opinion transistors are important.
If there are sub-circuits that you use more than once in the same schematic, or circuits you need to simulate with different simulators, please use Subcircuits.
FILES TO SUBMIT: a pdf file of the report; the archived project (to archive a project, go to the main ADS page, click on File→Archive Workspace, select the workspace to archive and decide where to save the file). Submit it on Learning Central in Assignments.
DEADLINE: Sun 23 Oct 2022, 11:59pm
Cardiff University – School of Engineering – Centre for High Frequency Engineering
