ECSE-4040 DIGITAL ELECTRONICS
FINAL EXAM, SPRING 2023
RENSSELAER POLYTECHNIC INSTITUTE
ASSIGNED: W, APRIL 12; DUE: W, APRIL 26
STATEMENT OF UNDERSTANDING
==============================================================================
“I understand that this Exam is officially administered under an Academic Honor Code: I hereby state that I have not used any other source material in completing this Exam other than my personal notes, the course notes, the course text, and/or SPICE software and documentation. In addition, I have not consulted or interacted, in any way or form, with anyone else, except, possibly, the Course Instructor, in completing this Exam.”
Name: _________________________________ (printed) Signature: _____________________________________
Student Number: _________________________ Date: ________________________________________
(Submit this signed page along with your work on LMS)
Note, for all SPICE simulations using MOS transistors, use the provided MOS2.txt file on LMS.
There are three problems on this exam. Use the given 130nm process parameters below for hand calculation for all problems where MOS transistors are used:
Problem 1 (30 pts. HAND, 10 pts. SPICE): | CMOS Logic & Delays |
Consider the circuit below with the given 130nm process transistor parameters with the four given input transitions. Reff values are given for a W/L = 1 scenario. Transistor W/L ratio is given in the schematic.
| • RNeff = 12.5 kΩ • RPeff = 30 kΩ • Cself = 1 fF/µm • Cg = 2 fF/µm • Cint = 0.1 fF/µm • L = 100 nm |
| 1. AB = 10 → 00 2. AB = 01 → 00 3. AB = 11 → 10 4. AB = 11 → 01 |
a) For all four input change scenarios, draw the equivalent Elmore Delay RC model for output node Y. Consider all transistors to have a constant resistance when on as given.
b) Propagation delay calculation:
i. For all four input scenarios, use your Elmore Delay RC models to derive and solve formulas for the propagation delay for node Y.
ii. Plot all 4 scenarios in LTSpice and state the simulated propagation delays. Compare these to your hand calculated results.
c) Consider the prior circuit with an inverter added at node Y. For all for input patterns, what is the new propagation delay at node Y, and the total propagation delay to ?
d) A 10 mm long wire is added at node . Considering this as a lumped, resistanceless capacitance, by hand calculate the delay for all four input change scenarios for nodes Y and .
e) If the widths of both transistors in the inverter were doubled, what happens to the propagation delays at nodes Y and ?
f) What is the logic function at node Y? What purpose does this logic function perform?
?
Problem 2 (20 pts. HAND, 10 pts. SPICE): | CML Logic & Fan out |
Consider the circuit below:
| • ISS = 1 mA • VEE = -5 V • RC = 250 Ω • ßF = 100 • VBE(FA) = 0.7 V • VBE(sat) = 0.7 V • VCE(sat) = 0.0 V |
a) Find VOH, VOL, VIH, VIL for the circuit above at output nodes X and Y considering a single input change.
b) Plot the VTC with and fixed to VOL, and B fixed to VOH. Plot both outputs X and Y, with input A ranging from VEE to 0, labelling VOH, VOL, VIH, VIL.
i. Plot both VX and VY by hand.
ii. Plot both VX and VY with LTSpice. Compare with hand results.
c) Find the noise margins, NMH and NML for outputs X and Y.
d) What are the logic functions at nodes X and Y?
e) What is the purpose of transistors Q5 and Q6? Why can’t inputs B and be input directly to Q1 and Q2, respectively?
f) Find the fan out, N, to input A, when NM’H = 0.
i. Calculate by hand.
ii. Verify fanout with LTSpice. Compare with hand results.
g) Consider the following modified circuit with the additional Q7 and Q8 transistors, with IEE = 1 mA:
i. What are the new VOH, VOL values?
ii. What is the new fan out, N?
Problem 3 (20 pts. HAND, 10 pts. SPICE): | SRAM Write |
Consider the following SRAM circuit with pre-charge and write circuitry with 130nm process parameters:
| • WP/L = 2.4 for all PMOS • WN/L = 1 for T3, T4, T5, T6 • WN/L = 10 for T9, T10 • L = 100nm • VDD = 1.2V |
a) Identify the transistors that would pass current to perform a write of logic 1 to the SRAM cell.
b) Assuming a successful write of logic 1, what states would these transistors be in?
c) Assuming a failed write of logic 1 (the transistors cannot pull Q,below VDD/2):
i. What states would the transistors responsible for a write of logic 1 be in?
ii. Solve by hand the voltage obtained at node . Assume = 0.
iii. Simulate this failed write in LTSpice.
iv. In LTSpice, modify transistor widths so that a functional write is obtained. What transistor widths did you modify, and why??
Submit your work on LMS under Final
• Show your work.
• Include images of your hand calculations with work and final results.
• Include screenshots of LTspice with all circuit schematics with all output plots.
• Due date: Wednesday, April 26th at 11:59pm.
