ECE626Winter 2023
ECE626 Final Project
Design of a Switched-Capacitor Filter
Deadline: March 22, Wednesday, 2023.
Target Specifications:
Design a switched-capacitor low-pass filter with the following specifications:
Parameter | Value |
Sampling Frequency | 15 MHz |
DC Gain | 0 dB |
Passband | 0 – 0.6 MHz |
Ripple in passband | < 0.25 dB |
Stopband | 1.2 – 7.5 MHz |
Gain in stopband | below -50 dB |
Minimum Capacitor Size | 0.05 pF |
Design requirements:
1. Determine the order of the filter. Derive H(z) and show the locations of zeros and poles in the z-domain.
2. Optimize the dynamic range and chip area.
3. Simulate the complete filter using macromodelsrepresenting the finite gain and BW of the op-amps.
4. Simulate the effects of charge injection, op-amp offset voltage, slew rate, bandwidth and finite gain in the performance of the filter. If necessary, modify the circuit to meet the specifications under practical conditions.
5. For extra credit, design the simplest stage of the filter on the transistor level, using e.g. opamp circuitry from earlier courses. Simulate to verify your high-level results.
CAD Tools:
You may use any CAD tools. Recommended practice:
1. Use MATLAB to calculate the filter order, zeros/poles and coefficients.
2. Use Cadence or Simulink to simulate the complete filter structure.
3. Use HSPICE and/or CADENCE for transistor-level simulations.
