# 程序代写案例-ECE626

ECE626 Project
Switched Capacitor Filter Design
Hari Prasath Venkatram
Contents
I Introduction 2
II Choice of Topology 2
III Poles an
d Zeros 2
III-ABilinear Transform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
IV Dynamic Range and Chip Area Scaling 5
V-A Linear Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
V-B High-Q section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
V-C Low-Q section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
V-D Opamp-Macro-Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
VI Charge Injection and Switches 15
VI-ASwitch Sizing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
VI-BCharge Injection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
VI-CChoice of W
L
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
VI-DChoice of Switch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
VI-EHarmonic Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
VI-F Clock-Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
VIIOffset 20
VII-AFirst Order Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
VII-BBiquad Low Q - Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
VII-CHigh-Q Biquad Stage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
VII-DFilter Offset Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
VIIISlew-Rate 22
IX Finite Gain 24
X CDS 27
XI Finite Bandwidth 27
XIIOpamp Design 31
I. Introduction
The Low pass switched-capacitor filter design is discussed. The first section discusses the choice of
topology to achieve the filter specification with minimum components and in a most economical way.
Second section discusses about the derivation of H(z) and the location of poles and zeroes in z-domain.
Section three discusses about dynamic range scaling and area scaling performed on this filter. Section
four discusses about the macro-model implementation of the filter. Section five discusses about the
various non-ideal effects in the switched-capacitor filter. Section six discusses the choice of opamp-
topology and the design of the opamp stage. Section seven concludes the report.
II. Choice of Topology
The specification for the low-pass filter is
Parameter Value
Sampling Frequency 100 MHz
DC Gain 0 dB
Passband 0-5 MHz
Ripple in Passband ≤0.2 dB
Stopband 10 -50 MHz
Gain in Stopband ≤ -50 dB
Minimum Capacitor 0.05 pF
The order of Butterworth filter required to meet this specification is 11.
The order of Chebyshev filter required to meet this specification is 6.
The order of Elliptic filter required to meet this specification is 5.
The most economical filter is elliptic filter.
III. Poles and Zeros
The Bilinear transform is used for the design of sampled-data filter from the analog counterpart.
The bilinear transform relationship between ’s’ domain and ’z’ domain is
Ωs =
2
T
tan(
ωT
2
)
This translates to the following pass-band and stop-band specification for the analog 5th order elliptic
filter. Sampling frequency is 100 MHz.
Ωpass = 200× tan(
pi
20
Ωstop = 200× tan(
pi
10
To give some margin, the filter was designed for 0.1 dB passband ripple and 51 dB stopband atten-
uation. The transfer function of the fifth order ’s’ domain filter is
H(s) =
0.003465s4 + 0.0009301s2 + 5.235× 10−5
s5 + 0.2725s4 + 0.07009s3 + 0.009836s2 + 0.0009921s+ 5.235× 10−5
The magnitude and phase response of the fifth order continuous-time elliptic filter is shown below.
The pole-zero map in ’s’ domain and z-plane are shown in the following figures. The transfer function
of the fifth order elliptic filter as a cascade of linear and biquad sections is given below.
0.5 1 1.5 2 2.5 3 3.5 4
−100
−80
−60
−40
−20
0
M
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in
d
B
5th Order Elliptic Filter in s−domain
0.5 1 1.5 2 2.5 3 3.5 4
−3
−2
−1
0
1
2
3
Ph
as
e
in
r
ia
ns
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9
−0.1
−0.05
0
F
ig
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5
t
h
O
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E
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F
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’s

d
o
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a
in
−0.1 −0.08 −0.06 −0.04 −0.02 0 0.02
−0.5
−0.4
−0.3
−0.2
−0.1
0
0.1
0.2
0.3
0.4
0.5
0.020.0420.070.10.140.2
0.3
0.55
0.1
0.2
0.3
0.4
0.1
0.2
0.3
0.4
0.020.0420.070.10.140.2
0.3
0.55
Pole−Zero Map
Real Axis
Im
ag
in
ar
y
Ax
is
F
ig
.
2
.
P
o
le
-Z
er
o
in
’s

d
o
m
a
in
A. Bilinear Transform
Trapezoidal intergration is a better approximation in integration. This approximation is used to
derive the bilinear s-to-z transformation.
sa =
2
T
z − 1
z + 1
This mapping was used to map s-domain poles to z-domain poles. The following tabular column
lists the s-domain and z-domain poles. The s-domain poles are normalized to 2/T.
Poles & Zeros s-domain z-domain
p1,2 -0.02027 ± 0.1695i 0.9075± 0.31699i
p3,4 -0.06725 ± 0.1179i 0.8513±0.20455i
p5 -0.0974 0.8224
z1,2 ± 0.4337i 0.68334± 0.73009i
z3,4 ± 0.2833i 0.85133± 0.52462i
z5 ∞ -1
The quality factor of s-domain poles are 4.2 and 1 respectively for the two complex poles. The pole
and zero closer to each other were used for forming the biquadratic section.
The z-domain transfer function is
H(z) =
0.003286z5 − 0.0068z4 + 0.004133z3 + 0.004133z2 − 0.0068z + 0.003286
z5 − 4.34z4 + 7.675z3 − 6.898z2 + 3.147z − 0.5828
The frequency response of the z-domain filter is shown in the following figure. The fifth-order transfer
function was designed as a cascade of a linear section and two second order sections. The transfer
functions of the linear and second order sections are given below. The poles and zeros closer to each
were used to form the biquadratic section.
H1(z) = 0.1486
z + 1
z − 0.822446
H2(z) = 0.1486
z2 − 1.70266z + 1
z2 − 1.81517z + 0.924196
H3(z) = 0.1486
z1 − 1.3666z + 1
z2 − 1.70274z + 0.76667
IV. Dynamic Range and Chip Area Scaling
The dynamic range scaling is performed to maximize the swing at each node of the filter. This
is performed by scaling the capacitors connected to the output of each opamp by peak gain of the
corresponding stage with respect to the input. All the capacitors that are either switched or connected
permanently to the output of the opamp is scaled by this factor. 
After performing dynamic range scaling for each output node, area scaling is performed at the input
terminal of each opamp. The smallest capacitor connected to the input of the opamp is scaled such
that, after scaling it has the minimum capacitor size. This order does not affect the dynamic range
scaling. Therefore, Dynamic range scaling is performed first and area scaling performed after dynamic
range scaling. The filter output before dynamic-range scaling is shown in the figure. 5
The dyamic range scaled output is shown in the figure. 6
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
−400
−350
−300
−250
−200
−150
−100
−50
0
Ph
as
e
(d
eg
re
es)
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
−120
−100
−80
−60
−40
−20
0
20
M
ag
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(d
B)
5th Order z−domain Elliptic Filter using Bilinear Transform
0.01 0.02 0.03 0.04 0.05 0.06 0.07 0.08 0.09
−0.1
−0.05
0
F
ig
.
3
.
5
t
h
O
rd
er
E
ll
ip
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c
F
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te
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in
’z

d
o
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a
in
−1 −0.5 0 0.5 1
−1
−0.8
−0.6
−0.4
−0.2
0
0.2
0.4
0.6
0.8
1
Real Part
Im
ag
in
ar
y
Pa
rt
Z−Domain Pole Zero Map
F
ig
.
4
.
P
o
le
-Z
er
o
in
’z

d
o
m
a
in
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
x 107
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
Frequency in Hertz(Hz)
M
ag
n
it
u
d
e
v
o
i
v
i
Individual Responses before DR Scaling
1 2 3 4 5 6
x 106
0.6
0.8
1
1.2
1.4
1.6
F
ig
.
5
.
M
a
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it
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e
R
es
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se
b
ef
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y
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m
ic
-R
a
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e
S
ca
li
n
g
0.5 1 1.5 2 2.5 3 3.5 4 4.5
x 107
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency in Hertz(Hz)
M
a
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n
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u
d
e
v
o
i
v
i
Dynamic Range Scaled Ouput
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5
x 106
0.92
0.93
0.94
0.95
0.96
0.97
0.98
0.99
1
F
ig
.
6
.
D
y
n
a
m
ic
R
a
n
g
e
S
ca
le
d
O
u
tp
u
t
A linear section and two biquadratic sections were used for simulating the z-domain transfer function.
Since one of the poles has a Quality factor of 4.2, a high-Q biquad structure was used for this section.
The following section explains the transfer function and the macro-model level implementation. The
first section is a low-pass filter to reject high frequency noise. The high-Q structure is placed in the
middle. This order was chosen to reduce sensitivity to power supply noise and fundamental noise.
A. Linear Section
The linear section was implemented as follows .
H1(z) = 0.1486
z + 1
z − 0.822446
The Linear section was implemented with the following structure. The dynamic range scaled and
area scaled capacitor values are shown in the figure 7.
B. High-Q section
The high-Q biquad was used for the pole with quality factor of 4.2. The transfer function imple-
mented using this structure is shown in the figure 8 .
H2(z) = 0.1486×
z2 − 1.70266z + 1
z2 − 1.81517z + 0.924196
The amount of capacitance spread is higher in a low-Q structure. This is because of the fact that
the large damping resistor Q
ω0
. This can be eliminated in the high-Q structure. The general transfer
function for the high-Q biquad is as follows.
H3(z) = −
(K3)Z
2 + (K1K5 +K2K5 − 2K3)z + (K3 −K2K5)
(1)z2 + (K4K5 +K6K5 − 2)z + (1−K5K6)
The above two expressions were compared to derive the values of Ki. Dynamic range scaling and Area
scaling was performed for the 5th order filter and the capacitor values are shown in the figure. For
clarity, single-ended version is shown. The implementation was done differentially.
C. Low-Q section
The low Q section was placed in the end. The transfer function implemented using this structure is
shown in the figure 9.
H3(z) = 0.1486
z2 − 1.3666z + 1
z2 − 1.70274z + 0.76667
The low-Q biquad is derived from its continuous-time counterpart Tow-Thomas Biquad. The resistors
are replaced with switched-capacitors and the structure is used for implementing the above transfer
function.
The general transfer function for this low-Q structure is shown below.
H3(z) = −
(K2 +K3)Z
2 + (K1K5 −K2 − 2K3)z +K3
(1 +K6)z2 + (K4K5 −K6 − 2)z + 1
−+
Vinp
Vo1p
Φ1
Φ
1
Φ
2
Φ2Φ2
Φ1C2
CA
Φ1
C3
Vinn C1
Vinp
Φ1
Φ
1
Φ2Φ2
C2
Vinn
C1
Φ
2
Φ1C3
CA
Vo1p Φ1
CA C2C1 C3Cap
Initial
DR
Area
(pF)
1 0.1807 0.3615 0.2158
1.6742 0.1807 0.3615 0.3614
0.4632 0.1000 0.1000 0.050
All Capacitor values in pF
Fig. 7. Linear Section
Comparing the above two expressions, the values ofKi, were determined and dynamic range scaling and
area scaling was performed. The corresponding Low-Q strucuture used in the 5th order elliptic filter is
shown in the following figure. Single-ended version is shown for clarity. However, implementation was
done in differential version. The Fifth-Order filter used for simulation with switch-sharing is shown in
the figure 10
D. Opamp-Macro-Model
The opamp macro-model used for the simulation of the filter is shown in the figure 11. The opamp
model was used to mimic the actual transistor level design with common mode feedback, finite gain,
bandwidth and slew rate limitation. The cascade of biquad sections and the linear section was simu-
lated in cadence with the opamp-macro model and boot-strap switches. The matlab ideal magnitude
response and the magnitude response from cadence simulations are shown in the figure. 12. The small
deviation(<0.01 mdB) is due to the significant number of digits used for the capacitor, opamp gain
− +
− +
+ −
+ −
V o
ff
V o
ff
V i
n
V o
1
V o
2
Φ
1
Φ
1
Φ
1
Φ
1
Φ
1
Φ
2
Φ
2
Φ
2
Φ
2
Φ2
Κ
1
Κ
5
Κ
4
Κ
6
Κ
3 C
1
C 2
K 1
K 3
K 4
K 5
K 6
C 1
C 2
Ca
p(p
F)
In
iti
al
D
R Ar
ea
Al
l C
ap
ac
ito
r v
al
ue
s
ar
e
in
p
F
0.
13
38
0.
14
86
0.
33
01
0.
33
01
0.
22
95
1.
00
1.
00
0.
22
41
0.
24
89
0.
31
44
0.
30
56
0.
21
86
0.
92
56
0.
95
21
0.
05
12
0.
05
0
0.
05
0
0.
07
19
0.
06
13
0.
21
17
0.
19
12
Fig.8.High-QSection
− +
− +
+ −
+ −
V o
ff
V o
ff
V i
n
V o
1
V o
2
Φ
1
Φ
1
Φ
1
Φ
1
Φ
1
Φ
2
Φ
2
Φ
2
Φ
2
Φ
2
Φ
2
Φ
1
Κ
1
Κ
5
Κ
4
Κ
6
Κ
3 C
1
C 2
K 1
K 3
K 4
K 5
K 6
C 1
C 2
Ca
p(p
F)
In
iti
al
D
R Ar
ea
0.
42
52
0.
19
39
0.
28
87
0.
28
87
0.
30
42
1.
00
1.
00
0.
40
49
0.
18
46
0.
28
87
0.
51
05
0.
30
42
1.
76
7
1.
00
0.
07
0
0.
05
0
0.
05
0
0.
13
82
0.
08
23
0.
30
61
0.
27
07
Al
l C
ap
ac
ito
r v
al
ue
s
ar
e
in
p
F
Fig.9.Low-QSection
−+
−+
V
o2p
V
o3p
Φ
1
Φ
1
Φ
1
Φ
1
Φ
1
Φ
2
Φ
2
Φ
2
Φ
2
Φ
2
Κ
1,1
Κ
5,1
Κ
4,1
Κ
3,1C1,1
C
2,1
Φ
1
Φ
1
Φ
2
Φ
2
Κ
1,1
Κ
6,1
Κ
3,1
Φ

2
C
1,1
V
o2n
Φ
1
Φ

2
Φ
2
V
o3n
C
2,1
−+
−+
V
o4p
Φ
1
Φ
1
Φ
1
Φ
1
Φ
1
Φ
2
Φ
2
Φ
2
Φ
2
Κ
1,2
Κ
5,2
C
1,2
C
2,2
Φ
1
Φ
1
Φ
2
Φ
2
Φ
1
Φ
2
C
1,2
V
o4n
Φ
1
Φ

2
Φ
2
C
2,2
Φ
1
Φ
2
Φ
2
Κ
6,2
Φ
2
Φ
1
V
o5p
V
o5n
−+
V
inn
Φ
1
Φ
1
Φ
2
Φ
2
C
2
V
inp
Φ
1
Φ
1
Φ
2
Φ
2
C
1
C
A
C
3
C
2
C
1
C
3
V
inp
V
inn
V
o1p
V
o1n
Κ
5,1
Κ
6,1
Κ
4,1
Κ
1,2
Κ
3,2
Κ
3,2
Κ
4,2
Κ
4,2
Κ
5,2
Κ
6,2
Fig.10.5
th
OrderEllipticFilter
vinn
vinp
vdiff
gmvdiff
gmvdiff
R C
R C

+
von
vop
von
vop
Vcm
Vcmfb
Vcmfb
Rc
Rc
Fig. 11. Opamp Macro-Model
and bandwidth.
VI. Charge Injection and Switches
A. Switch Sizing
Considering the model shown in the figure 13 for a typical switch. The voltage at the end of φ1 is
v(nT ) = vin(nT )(1− e

T
4RonC )
This voltage on the capacitor is discharged during φ2 into the virtual ground . The charging of the
feedback capacitor follows the similar expression. Hence the overall transfer function is
H(z) = −(1− e−
T
4RonC )2
Z−1
1− Z−1
For the error to be less than 0.1%, RC product should be less than T
15
. The largest capacitor is 0.6
pF. Switches were designed with minimum channel length. The sampling frequency is 100MHz.
Ron ≤
1
15fc0.6× 10−12
≤ 1.5kΩ
B. Charge Injection
The relation between Ron and qch is
Ronqch =
L2
µ
qch =
L2
Ronµ
=
15L2fcC
µ
Verror =
15L2fc
µ
0 0.5 1 1.5
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
M
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B
0.05 0.1 0.15 0.2 0.25 0.3
−0.1
−0.05
0

Matlab Response H(z)
50 dB Line
F
ig
.
1
2
.
M
a
tl
a
b
a
n
d
C
a
d
en
ce
P
lo
ts
Vin Ron Ron
Ron Ron
C
Vin
C
Φ1
Φ2 Φ1
Φ1
Φ1
Φ2
Φ2
Φ2

+
C

+
C
Fig. 13. Switch-Model
Substituting the values for fc,L and µ and assuming that half of the channel charge flows into the
capacitor, we get
Verror =
7.5× (0.18µ)2 × 100× 106
273.8× 108
= 0.825mV
C. Choice of W
L
The ON-resistance of the switch and the calculation of the switch size is shown below. The value of
ON-Resistance calculated before was used.
Ron =
1
µCox
W
L
(Vgs − Vtn)

W
L
=
1
2.738× 8.5× 10−5(1.8− 0.4)
≈ 3
⇒W ≈ 0.54µm
D. Choice of Switch
1.8V supply and 0.18µ TSMC model was used for simulations. To maximize the signal input to
the filter, transmission gates are preferred over stand-alone NMOS switches. The following switches
were compared for their performance. The harmonic distortion of each switch is compared, which
relates to the signal dependant charge injection and the non-linear ON-resistance of the switch. Clock-
feedthrough introduces a fixed amount of offset and hence should not introduce any harmonic dis-
tortion. The boot-strap switch has a fixed Gate-Source voltage, independent of the input voltage.
Hence, It introduces least amount of distortion to the signal. The estimated charge-injection due to
channel charge and clock-feedthrough was approximately 1.2 mV. The transient simulation shows the
pedestal of 1 mV for the bootstrap switch independant of the signal. Hence, Bootstrap switches were
used for the filter to minimize the distortion. The third harmonic distortion was at 89 dB below the
fundamental for a in-band signal tone.
E. Harmonic Distortion
The harmonic distortion at the output of each switch was simulated. The sampling frequency is
100MHz. The switches were sized according to the sampling bandwidth requirement. A single tone
at 3
64
× fs and 100mV peak amplitude with a common mode of 0.9 V was given at the input of each
switch. 64-point DFT was performed at the output of each switch. The following tabular column
shows the distortion performance of each switch.
Switch 1st(dB) 2nd(dB) 3rd(dB) 4rd (dB) 5th(dB)
NMOS + Dummy -20 -47.2 -58.23 -70.432 -81.7
Trans + Dummy -20 -65.2 -86.5 -94.6 -94.8
Bootstrap + Dummy -20 -86.08 -109.7 -118.8 -114.1
The following figure 16 shows the transient response of the five switches considered and the effect
of charge injection and clock feedthrough. This can be seen as a pedestal in the hold-mode. This
indicates the amount of charge injection resulting from channel charge and the clock-feedthrough.
The boot-strap switch has the least amount of charge-injection. The pedestal value is 1.2mV and is
independant of the input voltage.
F. Clock-Generator
The following non-overlapping clock generator was used for generating the clock-phases.
Vin Vin
Vin Vin
Vdd
Vdd
Cboot
C
C
CC
C
Φ1
Φ1
Φ1
Φ1
Φ1
Φ1
Φ1Φ1b Φ1b
Φ1b
Φ1b
Φ1b
Φ1b Φ1b
Φ1b
Vin
Sampling Switch
Fig. 14. Different Sampling Switches
Clk
Φ1
Φ2Φ2b
Φ1b
Fig. 15. Non-Overlapping Clock Generator
VII. Offset
The Effect of offset was simulated with Vin=0 and a input referred opamp offset voltage of 1 mV.
The following estimates were used in determining the effect of the offset of each stage of the filter .
A. First Order Stage
During Steady state, the charge entering the virtual node due to the capacitors which are switched
must be zero. Hence
−VoffC2 + (Vo1 − Voff )C3 = 0
⇒ Vo1 = Voff1(
C2
C3
+ 1)
Assuming 1 mV offset and using the values of C2 = 362fF, C3 = 215fF , The value of the steady state
output voltage due to offset is 2.65 mV. This can be observed from the simulation result also.
B. Biquad Low Q - Stage
The effect of input referred offset voltage was simulated with Vin=0 and an input referred opamp
offset voltage of 1 mV. The following estimates were used in determining the effect of the offset.
−VoffK1 + (Vo1 − Voff)K4C1 = 0
⇒ Vo1 = (
K1
K4
+ 1)Voff
= 2.475mV
For the intermediate node of the low-Q biquad, the effect of the offset is derived as follows,
−VoffK5 + (Vo1 − Voff)K6 = Vo2K5
Vo2 = (Vo1 − Voff)
K6
K5
− Voff
= 0.49mV
The effect of offset voltage was simulated with Vin=0 and an input referred opamp offset voltage of
1 mV. The following equations were used in determining the effect of the offset.
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
x 10−7
0.82
0.84
0.86
0.88
0.9
0.92
0.94
0.96
0.98
1
Time in second(s)
V
ol
ta
ge
(V
)
Sample and Hold Output and Charge Injection

1.06 1.07 1.08 1.09 1.1 1.11
x 10−7
0.904
0.906
0.908
0.91
0.912
0.914
0.916

Input
NMOS
TRANS−Gate + Dummy
TRANS−Gate
Bootstrap +Dummy
NMOS +Dummy
Bootstrap
F
ig
.
1
6
.
T
ra
n
si
en
t
O
u
tp
u
t
R
es
p
o
n
se
−K1Voff +K4Vo2 −K4C1 = 0
Vo2 = (1 +
K1
K4
)Voff
= 1.432mV
Vo1 = Voff
= 1mV
Transient simulation was performed with input referred offset and the steady state output voltages are
shown in the figure. The simulated steady state values and the estimated values match.
D. Filter Offset Voltage
The following equations were derived for the steady filter output voltage with input referred offset
in each opamp. The derivation is from the first order section.
Vo1 = (1 +
C2
C3
)Voff = 2.67mV
Vo2 = −Voff = 1mV
Vo3 = Voff −
K1,2
K4,2
(Vo1 − Voff ) = 0.4mV
Vo4 = (Vo5 − Voff)
K6,3
K5,3
− Voff = −0.05mV
Vo5 = Voff −
K1,3
K4,3
= 2.475mV
Ki,j represents the coefficient i in the section j.
VIII. Slew-Rate
The slew rate is caused by the opamp’s maximum current output. Thus, the rate at which the
output node is charged is fixed at a particular rate. For a sinusoidal input, the rate of increase of the
input is
SR =
dvin
dt
= Vpωin
The maximum slew-rate occurs at maximum passband frequency and peak amplitude. Therefore, the
maximum step in one time period is
∆v = VpωinT
∆v
∆t
=
VpωinT
aT/2
=
2Vpωin
a
The maximum-rate at 1V-Differential input at 4.687 MHz is around 160V/µs.
This could be seen from the distortion spectrum at the output of the filter. The distortion spectrum
in shown in the figure. 19.
0 0.5 1 1.5 2 2.5 3
x 10−6
−4
−3
−2
−1
0
1
2
3 x 10
−3
Time in second(s)
O
ut
pu
t V
ol
ta
ge
(V
)
Transient Output of Individual Stage with Opamp Offset
0 0.5 1 1.5 2 2.5 3
x 10−6
−3
−2
−1
0
1
2
3
4
5 x 10
−3
Time in second(s)
Tr
an
si
en
t S
et
tlin
g
O
ut
pu
t V
ol
ta
ge
(V
)
Filter Transient with Opamp Offset Voltage
−2.6 mV
0.4 mV
0.05 mV
1 mV
2.475 mV
Fig. 17. Individual and Filter Offset Voltage
−+
Vinp
Vo1p
Φ1
Φ
1
Φ
2
Φ2Φ2
Φ1C2
CA
Φ1
C3
Vinn C1
Fig. 18. Slew-Rate Estimation
Slew-Rate - Method 2
The Linear section has the worst-case slew-rate limitation. Consider the linear section shown in the
figure 18. Assuming the opamp has 20% of one-clock phase to slew and maximum input of 1 V, The
worst-case slew-rate is derived as follows,
∆qin = vin(C1 + C2)
∆vout =
C1 + C2
C3 + CA
vin
SRmax =
0.2vin
0.5× 0.2× T/2
⇒ SRmax = 400V/µ s
Slew-Rate Fundamental(dB) 3rd(dB) 5th(dB)
50V/µs 2 -22 -34
100V/µs 2 -40 -50
150V/µs 2 -75 -85
200V/µs 2 -78 -87
The distortion for slew-rates greater than 150V/µs is limited mostly by the switch-non linearity. To
give a safety margin of 30V/µs, The slew-rate required for the opamp is 180V/µs.
IX. Finite Gain
The Effect of finite gain was analyzed with respect to the integrator , . The effect of finite DC
gain on the poles of the filter is considered. The Integrator transfer function with finite DC gain is
given by
H(z) =
−C1Z
(C2 +
C1+C2
A0
)Z − C2(1 +
1
A0
)
Z ≈ 1 + sT
H(s) =
−C1(1 + sT )
(C2 +
C1+C2
A0
)(1 + sT )− C2(1 +
1
A0
)
=
−C1
C2T
s+ C1
C2AT
0.5 1 1.5 2 2.5
x 107
−100
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
Frequency in Hertz
M
ag
ni
tu
de
in
d
B
Distortion due to Slew−Rate

SR = 50 V/µ s
SR = 100 V/µ s
SR = 150 V/µ s
SR =200 V/µ s
F
ig
.
1
9
.
D
is
to
rt
io
n
d
u
e
to
S
le
w
-R
a
te
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
x 107
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
Frequency in Hertz(Hz)
M
ag
ni
tu
de
R
es
po
ns
e
in
d
B
Effect of Finite Gain(100−1000) and Bandwidth 500MHz
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
x 106
−0.6
−0.4
−0.2
0
F
ig
.
2
0
.
F
in
it
e
G
a
in
E
ff
ec
t
Assuming the DC gain as 1000 and highest pole frequency as 5 MHz, the normalized pre-distortion
value needed is pi
20000
. The pre-distorted poles are given by
Pole Ideal Pre-Distorted
1,2 -0.0168 ± 0.1650i -0.0160 ± 0.1650i
3,4 -0.0575 ± 0.1151i -0.0570 ± 0.1151i
5 -0.0848 -0.0840
The effect of finite DC-gain changes s to s+σ. The effect of this can be analyzed in the biquad.
The Denominator in the biquadratic transfer function changes to
s2 + (
ω0
Q
+ σ1 + σ2)s+ (ω
2 +
ω0σ1
Q
+ σ1σ2)
The new pole Q’ can be compared with ideal transfer function.
ω0
Q′
=
ω0
Q
+ σ1 + σ2

1
Q′
=
1
Q
+
1
ω0AT
(
C1
C2
+
C ′1
C ′2
)
The effect of DC-gain will be large in a high Q. The elliptic filter has two biquads. The quality factor
is approximately 1 and 5. Hence the pass-band deviation due to the finite gain can be derived as
σ1 ≈ σ2 ≈
1
A0
∆Rp = 1 +
2Q
A0
For the given passband ripple of 0.2 dB, the minimum DC-gain required for the high-Q biquad is
≥ 54 db approximately. To have some margin due to variation in DC-gain, 60 dB DC-Gain was chosen
for the opamp used in the filter. The finite-dc gain affects the passband poles with high-Q. This can
be clearly observed in the figure. 20. The effect of scaling with finite opamp gain is shown in the
figure. 23. We can see that the dynamic range scaled system is more close to ideal response when
compared with unscaled filter response.
The predistorted and ideal response is shown in the figure. 22.
X. CDS
The finite gain error and phase error in the integrator can be minimized using CDS or CLS. The
CDS integrator shown in the figure 21 has a constant gain error and is independant of the frequency .
The integrator and the charge transfer expression are given in the figure 21
XI. Finite Bandwidth
The finite bandwidth effect with a single-pole finite DC gain amplifier.
Av(s) =
s
ωp
+ 1
Where ωpAdc is the unity gain bandwidth of the integrator , . The solution for integrator is shown
below . The approximate transfer function is Finite Gain and bandwidth effect is modelled for an
−+
C2
C3
C1Vin
Φ2
Φ1
Φ1
Φ1
Φ2
Φ1
Φ1
C1 C2 C3
Vin(n-1) +V0(n-1)/A V0(n-1)(1+1/A) V0(n-1)
V0(n-1/2)(1/A)Φ2 V0(n-1)(1+1/A) V0(n-1/2)(1+1/A)
Φ1 Vin(n) +V0(n)/A V0(n)(1+1/A) V0(n)
Φ
C
Fig. 21. CDS- Integrator
Integrator. Single-pole amplifier is assumed with finite DC Gain.
Vo(Z)
Vi(Z)
=
Z−1
1− Z−1
Vo(Z)
Vi(Z)
=
(1− δ)Z−1
1− (1− 1
)Z−1
Where δ = (1− k(1− e−ω0T/2))e−ω0T/2,k=feedback factor. ω0 - unity gain bandwidth.
k is the feedback factor. This manifests itself as a gain error in the integrator. To minimize the effect
of finite bandwidth, δ must be much smaller than the permissible tolerance of C1
Ci
. Thus, the unity gain
frequency is approximately 4-5 times the clock frequency. However, Choosing a higher bandwidth will
result in folding of noise. The effect of bandwidth is shown in the figure.25
0 0.5 1 1.5 2 2.5 3 3.5
−120
−100
−80
−60
−40
−20
0
20
M
ag
ni
tu
de
in
d
B
Ideal and Predistorted Response
0.05 0.1 0.15 0.2 0.25 0.3
−0.1
−0.05
0
0.05
F
ig
.
2
2
.
P
re
d
is
to
rt
ed
a
n
d
Id
ea
l
R
es
p
o
n
se
-
P
a
ss
b
a
n
d
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
x 107
−80
−70
−60
−50
−40
−30
−20
−10
0
Frequency in Hertz(Hz)
M
ag
ni
tu
de
R
es
po
ns
e
in
d
B
Effect of Finite Gain(1000) in DR scaled and unscaled Response
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
x 106
−0.15
−0.1
−0.05
0

Ideal
Scaled
Unscaled
F
ig
.
2
3
.
P
re
d
is
to
rt
ed
a
n
d
Id
ea
l
R
es
p
o
n
se
-
P
a
ss
b
a
n
d
Vin
C1
Φ1
Φ2 Φ1
Φ2

+
C2
A
Fig. 24. Finite Bandwidth Effect
XII. Opamp Design
Folded-cascode opamp was chosen for the opamp-design. In-order to maximize the output swing
and to minimize the any extra compensation capacitors, folded cascode opamp was chosen . The
figure 26 shows the magnitude response of the top-level simulation of the 5th order elliptic filter with
bootstrap switches and folded-cascode opamp. The Ideal response and the macro-model response with
finite gain and bandwidth limitations are also shown for comparison. The opamp designed has the
following specifications.
Parameter Value
DC-Gain 57.8 dB
Unity Gain Bandwidth 500 MHz
Slew-Rate 180V/µs
Common-mode 0.9 V
The above specifications were derived from the finite-DC gain and bandwidth requirements for the
filter specification. The open-loop gain and bandwidth characteristics of the amplifier is shown in the
figure. 27.
From the bandwidth requirement, the input pair transconductance is calculated.
gm,in
CL
= 2pi × 500× 106
With effective load capacitance of 1 pF, the transconductance required is 3.14 mS. The bias current
required was estimated from the slew-rate requirement. The opamp was over-designed for the slew-rate
requirement. The opamp is capable of handling slew-rate of 400V/µs. The bias current was 410µA
for the tail current source. The fully differentially opamp schematic is shown in the figure ??. The
overdrive is 100 mV. The opamp is capable of 2.8 Vp−p differential swing. Thus, the dynamic range of
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
x 107
−80
−70
−60
−50
−40
−30
−20
−10
0
10
Frequency in Hertz(Hz)
M
ag
ni
tu
de
R
es
po
ns
e
in
d
B
Effect of Finite Gain(1000) and Bandwidth 50MHz − 500MHz
0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
x 106
0
0.5
1
1.5
2
Increasing Bandwidth
F
ig
.
2
5
.
F
in
it
e
B
a
n
d
w
id
th
E
ff
ec
t
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
x 107
−90
−80
−70
−60
−50
−40
−30
−20
−10
0
Frequency in Hertz(Hz)
M
ag
ni
tu
de
in
d
B
5th Order Elliptic Filter with Folded Cascode Opamp

0.5 1 1.5 2 2.5 3 3.5 4 4.5 5
x 106
−0.15
−0.1
−0.05
0
Ideal
Bootstrap Switch + Folded−Cascode Opamp
Bootstrap Switch + Macro−Model Opamp
−50 dB Line
DC−Gain = 0.9954
F
ig
.
2
6
.
T
o
p
-L
ev
el
S
im
u
la
ti
o
n
o
f
F
il
te
r
100 101 102 103 104 105 106 107 108 109 1010
−20
0
20
40
60
Frequency in Hertz
O
pe
n
Lo
op
G
ai
n
in
d
B
Open Loop Amplifier Gain and Phase

−200
−150
−100
−50
0
Gain
Phase
46° Phase Margin
57.8 dB DC Gain
F
ig
.
2
7
.
O
p
en
-L
o
o
p
A
m
p
li
fi
er
G
a
in
a
n
d
P
h
a
se
C
h
a
ra
ct
er
is
ti
cs
Vdd
Vb1
Vb2
2.5 KΩ
55 µA
2.8 KΩ
Vb3
Vb4
V+
V
-
M0 M1
M3 M4
M5 M6
M7
Vb2
Vb4
Vb4
VcmfbVcmfb
VopVon
Vop
Von Vcm
1/gm2 1/gm2
Cc
Cc
M25
M8
M9 M10
M12
M11
M13 M14
M15 M16 M17
M18M19 M19
M23 M24
M20
M21
Transistor Sizes in µm
M3,M5,M4,M6 26(0.5/0.5) M7,M8,M25,M0,M1,M13-16 80(0.5/0.5)M9,M10 468(0.5/0.5) M11,M12 234(0.5/0.5)
Common-mode Feedback branch Current density is 1/5th of the differential branch
- - - -
F
ig
.
2
8
.
T
ra
n
sisto
r
L
ev
el
S
ch
em
a
tic
the filter is maximized. The opamp was design using 0.18µ TSMC model at 1.8 V supply. The total
bias current consumption is 1.1 mA.
The impulse-response and step response of the transistor level filter(Opamp + Bootstrap Switch) is
compared with Ideal filter in the figure 30. The transient simulation with 2 Vp−p input at 500 kHz is
shown in the figure 31. The clippin near 1 V is due to limitation of the swing at around 1.4 V and at
0.5 V of the folded cascode amplifier.
References
 R. Gregorian and G. C. Temes, Analog MOS Integrated Circuits for Signal Processing. Wiley Series on Filters, 1986.
 D. A. Johns and K. Martin, Analog Integrated Circuit Design. Wiley, 2005.
 G. C. Temes, “Finite amplifier gain and bandwidth effects in switched-capacitor filters,” IEEE JOURNAL OF SOLID-STATE
CIRCUITS., vol. 15, pp. 358–361, 1980.
 K. Martin and A. S. Sedra, “Effects of the op amp finite gain and bandwidth on the performance of switched-capacitor filters,”
IEEE Transactions on Circuits and Systems., vol. 28, pp. 822–829, 1981.
 G. C. T. K. Haug, F. Maloberti, “Switched-capacitor integrators with low finite-gain sensitivity,” Electronic Letters, vol. 21,
pp. 1156–1157, 1985.
 R. Gregorian, Introduction to CMOS Op-Amps and Comparators. Wiley, 1999.
2 4 6 8 10 12 14 16
x 10−7
−0.04
−0.02
0
0.02
0.04
0.06
0.08
0.1
Time in second(s)
T
r
a
n
s
i
s
t
o
r

L
e
v
e
l

F
i
l
t
e
r

R
e
s
p
o
n
s
e
(
V
)
Impulse response of Transistor Level Filter
2 4 6 8 10 12 14 16
x 10−7
−0.04
−0.02
0
0.02
0.04
0.06
0.08
0.1
Time in second(s)
I
d
e
a
l

F
i
l
t
e
r

R
e
s
p
o
n
s
e
Impulse response of Ideal Filter
F
ig
.
2
9
.
Im
p
u
lse
R
esp
o
n
se
1 2 3 4 5 6 7 8 9 10
x 10−7
0.2
0.4
0.6
0.8
1
Time in second(s)
S
t
e
p

R
e
s
p
o
n
s
e

o
f

T
r
a
n
s
i
s
t
o
r

L
e
v
e
l

F
i
l
t
e
r
(
V
)
Step Response of Ideal Filter and Transistor Level Filter
1 2 3 4 5 6 7 8 9 10
x 10−7
0
0.2
0.4
0.6
0.8
1
Time in second(s)
S
t
e
p

R
e
s
p
o
n
s
e

o
f

I
d
e
a
l

F
i
l
t
e
r
(
V
)
F
ig
.
3
0
.
Im
p
u
lse
R
esp
o
n
se
0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2
x 10−5
−1.5
−1
−0.5
0
0.5
1
1.5
Time in Second(s)
T
r
a
n
s
i
e
n
t

R
e
s
p
o
n
s
e
Transient response of 2Vp−p Input sinusoid at 500 kHz with Transistor Level Opamp + Switch

Input
Filter Output
F
ig
.
3
1
.
T
ra
n
sien
t
R
esp
o
n
se Email:51zuoyejun

@gmail.com