Kings College London 

This paper is part of an examination of the College counting towards the award of a degree. 

Examinations are governed by the College Regulations under the authority of the Academic Board. Degree Programmes Module Code Module Title BEng, MEng 6CCS3HAD Hardware Design Examination Period Time Allowed 2 hours ANSWER EACH QUESTION ON A NEW PAGE OF YOU ANSWER BOOK AND WRITE ITS NUMBER IN THE SPACE PROVIDED Notes Calculators Books, notes or other written material may not be brought into this examination Calculators may be used. The following models are permitted: Casio fx83 Casio fx85 May 2021 (Period 2) A VHDL DATASHEET HAS BEEN INCLUDED AT THE END OF THIS PAPER PLEASE DO NOT REMOVE THIS PAPER FROM THE EXAMINATION ROOM S E C T I O N: A This section includes multiple-choice questions, and only one choice is the correct answer. 1. Which of the following is a legal VHDL identifier? A. 123A B. A123_ C. c1__c2 D. and1 2. In the following VHDL code, E, F, G, and H are integers that are 0 at time 10ns. If H changes to 1 at 20 ns, specify the times at which G will change. [3 marks] Process (H) Begin E <= 1 after 5 ns; F <= E + 1; G <= F after 10 ns; End process; A. 30 ns B. 20 ns C. 10 ns D. None of the above [3 marks] 3. Why is abstraction an essential part of engineering design? A.Without abstraction all schematics would be drawn at the transistor-level. B.Abstraction allows computer programs to aid in the design process. C.Abstraction allows the details of the implementation to be hidden while the higher-level systems are designed. Without abstraction, the details of the implementation would overwhelm the designer. D. Abstraction allows analog circuit designers to include digital blocks in their systems. [3 marks] 4. In a decoder, a logic expression is created for each output. Once all of the output logic expressions are found, how can the decoder logic be further minimized? A. By using K-maps to find the output logic expressions. B. By buffering the inputs so that they can drive a large number of other gates. C. By identifying any logic terms that are used in multiple locations (inversions, product terms, and sum terms) and sharing the interim results among multiple circuits in the decoder. D. By ignoring fan-out. [3 marks] 5. What allows a finite state machine to make more intelligent decisions about the system outputs compared to combinational logic alone? A. A finite state machine has knowledge about the past inputs. B. The D-Flip-Flops allow the outputs to be generated more rapidly. C. The next state and output logic allow the finite state machine to be more complex and implement larger truth tables. D. A synchronous system is always more intelligent. [3 marks] 6. For the circuit in the figure, the NOT gate has a delay of 10ns and the AND gate has a delay of 15ns. At t=0, there is a 0 1 transition at the input. At the output, you will observe A. a 01 transition at 15ns and 10 transition at 25ns B. a 01 transition at 25ns and 10 transition at 35ns C. a 01 transition at 15ns and 10 transition at 20ns D. none of the above 7. Three snippets of VHDL codes are shown below: I. z<=xafter4ns II. z <= transport x after 4 ns III. z <= reject 4 ns x after 4 ns Which of the above correspond to the waveform patterns shown below? [3 marks] A. I and II. B. II and III. C. I and III. D. Only I. E. None of the above. [3 marks] 8. An S-R latch has been constructed using two NOR gates which have unequal propagation delays of 10 ns and 20 ns as shown. At t=0, there is a 10 transition at the R input. S=0 throughout. Which of the following is true? A. Q changes to 1 at 10 ns and Qbar changes to 0 at 10 ns B. Q changes to 1 at 10 ns and Qbar changes to 0 at 20 ns C. Q changes to 1 at 10 ns and Qbar changes to 0 at 30 ns D. Q and Qbar remains unchanged. E. None of the above [3 marks] 9. In the VHDL code for an SR latch shown below, one of the lines is incorrect. architecture dataflow of SR_latch is begin Q <= '1' when R = '0' else '0' when S = '1' else unaffected; Qbar <= '1' when S = '0' else '0' when R = '0' else unaffected; end architecture dataflow; The corrected version of that line is A. '0' when S = '0' else B. '0' when R = '1' else C. Q <= '0' when R = '0' else D. Qbar <= '0' when S = '0' else E. None of the above 10. The circuit implementation of an FSM is shown below. The input x that arrives at this circuit is triggered by the clock, and it is 0110 as shown. Initially, Q=0.The transitions in X occurs with [3 marks] the same delay with respect to the rising edge of the clock in each cycle. The output of the circuit is A. 0010 B. 0100 C. 0110 D. None of the above. S E C T I O N: B Answer all the questions from this section. 11. Implement the following VHDL code using these components: D flip-flops with clock enable, a multiplexer, and adder, and any necessary gates. Assume that Ad and Ora will never be 1 at the same time, and only enable the flip-flops when Ad or Ora is 1. [3 marks] Library IEEE; Use IEEE. numeric_bit.all; Entity module1 is Port (A, B: in unsigned (2 down to 0); Ad, Ora, clk: in bit; C: out unsigned (2 down to 0)); End module1; Architecture RT of module1 is Begin Process(clk) Begin If clk = 1 and clk event then If Ad = 1 then C <= A + B; end if; If Ora = 1 then C <= A or B; end if; end if; end process; end RT; [8 marks] 12. (a) Show how you could use the generic and generate statements to model an n-bit ripple adder. Write the full entity and architecture description of your ripple adder. You may assume that the entity FullAdder, modelling a 1-bit full adder, has already been analysed into the working library and may be used in a higher-level entity. [6 marks] (b) Write a VHDL template for a testbench which could be used to test the VHDL model of the ripple adder. You do not have to write detailed VHDL code inside your template, but you must provide full comments of the function of each element of the testbench. [6 marks] 13. You are part of a design team on a project to build a controller for a plant. As one of the resident VHDL experts, you are required to construct a VHDL model of a 8-to-256 binary decoder which will form part of the overall digital electronic components of the system. The specifications team have already written the entity declaration for the decoder, which is given below: entity DECODER8to256 is port( I :in std_logic_vector(7 downto 0); EN :in std_logic; Y :out std_logic_vector(255 downto 0) ); end; The output of the decoder, Y, is set to 1 in bit (255 k) if and only if the input code word I is the binary representation of k and the enable pin EN is set to 0. The least significant bit of Y is bit position zero. A few entries of the truth table have been reproduced below (Table 1): I 00000000 00000001 00000010 00000011 EN Y (256 bits) 0 10000 ... 000000 0 01000 ... 000000 0 00100 ... 000000 0 00010 ... 000000 (a) ......... 11111111 0 00000 ... 000001 xxxxxxxx 1 00000000000000 Table 1 Explain when and how conversion functions are used to convert between certain common array types in VHDL. [4 marks] (b) Describe an efficient method in VHDL of setting the (255 k)th bit in the 256-bit vector Y. [3 marks] (c) Write a VHDL architecture description for the decoder entity given above. [6 marks] (d) Write a test bench for the decoder using a signal OK of type Boolean to indicate whether the model is behaving correctly. Ensure the test bench tests for both states of the Enable pin. [7 marks] 14. You are tasked with the design of a pseudorandom number generator which creates the following sequence of numbers (in binary): 0 32103210... and so on in a clock triggered fashion. There are no inputs to the system other than the clock. (a) How many bits are required to encode the states and the outputs? [2 marks] (b) Construct a State Table showing the current states, next states, and the outputs. Give one possible state assignment for the above system. [4 marks] (c) Write the state equations and draw a circuit implementation of the FSM using D Flip-Flops and logic gates. [8 marks] (d) Is this a Mealy machine or a Moore machine? Draw the state diagram and algorithmic state diagram. [8 marks] (e) Build a full VHDL model for the state machine using separate processs for decoding the outputs and states. Include both the entity and architecture descriptions. [8 marks] VHDL Datasheet Final Page