ECE 264A: Analog Integrated Circuits and Systems I Ian Galton February 15, 2022 EBU1 5606 Homework Assignment 5 Due: 5 pm, February 24, 2022 </br> 1. Solve the attached 2009 ECE264A second midterm exam 2. Solve the attached 2010 ECE264A second midterm exam 3. Solve the attached 2013 ECE264A second midterm exam 4. Solve the attached 2007 ECE264A final exam Each of the exams was given as a closed-book exam. The midterm exams had a time limit of 1 hour and 20 minutes, and the final exam had a time limit of three hours. It is suggested that you study for the upcoming ECE264A midterm exam prior to working on the problems. Then try to do the problems under conditions that simulate the exam conditions (i.e., without using books or class notes and with the goal of completing each set of exam problems within the allotted time.) ECE 264A CMOS Analog Integrated Circuits and Systems Midterm Exam 2, March 2, 2009 2 This problem relates to the following output buffer circuit: In solving each part you may assume that: (i) the transistors are in saturation, (ii) rds in each transistor’s small-signal model circuit may be neglected (iii) the two bias current sources are ideal (iv) the small-signal model of each op-amp is ( ) 1 m d a G v s s Z (v) All capacitances except Ca, CS, and CL may be neglected. a) (20 points) Draw the small-signal model of the differential-mode (DM) half circuit. Be sure to justify the use of half-circuit analysis. b) (20 points) Derive a block diagram of your DM small-signal model half circuit with input vi1(s), and nodes corresponding only to the gate and source voltages (to ground) of the transistor. c) (20 points) Derive an expression for the DM gain of the overall circuit. You need not factor or otherwise simplify your answer. However, in addition to ensuring the units of your expression are correct, apply one or more simple “sanity checks” to determine whether your expression has any obvious errors. d) (20 points) Use your result from Part b) to plot the magnitude and phase of the loop gain using the asymptotic approximations presented in class for parameter values: Gm = 10í3 ȍí1, gm = 10í3 ȍí1, Ȧa = í109 rad/s, ra = 2×106 ȍ, RL = 103 ȍ, RS = 2×103 ȍ, Ca = 50 fF, CS = 100 fF, and CL = 10 pF. Roughly estimate the phase margin form your plots. e) (20 points) Suppose you are asked to add one or more capacitors to the original circuit to implement dominant pole compensation for a phase margin of 600 assuming the parameter values given in Part d). Calculate the required size of the capacitors and explain how you would connect them to the original circuit? ECE 264A CMOS Analog Integrated Circuits and Systems Second Midterm Exam, March 9, 2010 2 The following problems relate to the amplifier circuit shown below. In solving each problem, you may assume that (i) Capacitances CC and CL are sufficiently large that the small-signal transistor model capacitances may be neglected, (ii) all transistors are in saturation, (iii) all the current sources are ideal, and (v) 1/ i jds m r g for all values of i and j. Vin M1 M2 VoutIBIAS 2 IBIAS 1 CL R2R1 CC 1) Derive a block diagram of the circuit with input vin(s), output vout(s), and nodes corresponding to vgs1(s) and vds1(s). Do not include any other nodes in your block diagram. 2) Derive an expression for Av(s) = vout(s)/vin(s) using the Asymptotic Gain Relation. Explain whether your answer is consistent with the block diagram you derived for Part a). 3) Derive an expression for the loop gain, T(s), directly from the small-signal model representation of the circuit (not using the block diagram you derived or the Asymptotic Gain Relation). 4) Suppose R1 = 2 kȍ, R2 = 8 kȍ, gm1 = 2·10í3 ȍí1, rds1 = 200 kȍ, gm2 = 10í4 ȍí1, rds2 = 1 Mȍ, CC = 300 fF, and CL = 3 pF. Calculate the phase margin of the circuit. 5) Choose a new value for CC that results in a phase margin of 65 degrees. ECE 264A CMOS Analog Integrated Circuits and Systems Second Midterm Exam, March 7, 2013 2 This problem relates to the following amplifier circuit where (i) M1 and M2, are identical, M3 and M4 are identical, M5 and M6 are identical, M7 and M8 are identical, and M9 and M10 are identical, (ii) M5 has the same length but 4 times the width of M3, (iii) M7 has the same length but 4 times the width of M1, (iv) M9 has the same length but half the width of M1, (v) 1m g = 5·10–4 ȍ–1, 3m g = 5·10–4 ȍ–1, (and recall that 2 , 1,2, , 10 im i Di g k I i ! ) (vi) 6 8ds ds r r = 200 kȍ, and (vii) 1gs C = 90 fF, 3gs C = 100 fF (and recall that igs C is proportional to the transistor width). (viii) You may assume: all capacitances except Cgs in each of M1 through M8 may be neglected, all the capacitances in M9 and M10 may be neglected, the two current sources are ideal, and 1/ i jds m r g for all values of i and j. I M1 Vi1 M2 M4 Vi2 M3 M5 M6 M7 M8 Vo1 Vo2 M9 M10 1pF 1pF I/2 1. (40 points) Derive an expression for the for the Laplace Transform of the differential mode gain, Adm(s), of the circuit (note: given (viii) above, you may assume that there are no zeros, so this need not be an algebra-intensive problem) 2. (40 points) If the op-amp were connected in a feedback configuration where the open loop gain is a(s) = Adm(s), and the feedback factor is f(s) = 0.2, what would be the phase margin of the feedback system (assume that the op-amp sees no additional loading beyond the 1 pF capacitors shown in the figure). 3. (20 points) Calculate the phase margin of the common mode feedback circuit in the amplifier (assume that the op-amp sees no additional loading beyond the 1 pF capacitors shown in the figure). ECE 264A: CMOS Analog Integrated Circuits and Systems I Final Exam, March 22, 2007 2 1. (80 points) This problem relates to the following amplifier circuit. In solving each part, you may assume that (i) Transistors M1 and M2 are identical, and transistors M4 and M5 are identical, (ii) Capacitances CI and CL are sufficiently large that the small-signal transistor model capaci- tances may be neglected, (iii) all transistors are in saturation, (iv) the current source symbols denote ideal current sources (v) rds1 and rds2 can be neglected, (vi) rds4 1/gm4 and rds5 1/gm5, (vii) the voltage VREF is held constant by circuitry not shown in the figure, and (viii) the input signal has the form Vin = VREF + vin, where vin is a small-signal variation about VREF. a) Carefully draw the small signal model of the circuit (simplified using assumptions (i) through (vii) where appropriate). b) Derive a block diagram for the circuit with nodes corresponding to the following variables: vin, 2d v , and vout. c) Use Mason’s Gain Formula to derive an expression for Av(s) = vout(s)/vin(s). d) Derive an expression for Av(s) = vout(s)/vin(s) using the Asymptotic Gain Relation. Verify that your answer is consistent with the block diagram you obtained in solving Part b). e) Determine an expression for the loop gain, T(s), by breaking the feedback loop in your small signal model of the circuit (not the block diagram). If possible, use techniques presented in class to do this with little or no algebra. f) Suppose R1 = 2 kȍ, R2 = 8 kȍ, gm1 = gm3 = 10í3 ȍí1, rds3 = rds5 = 200 kȍ, and CL = 0.1 pF. Calculate the required value of CI that results in a phase margin of 65°. ECE 264A: CMOS Analog Integrated Circuits and Systems I Final Exam, March 22, 2007 3 2. (20 points) Suppose a feedback loop has a loop gain given by 3 6 3 1 /100 ( ) 10 1 s T s s Determine whether the feedback loop is stable using whichever of the following techniques is appropriate: phase margin analysis, gain margin analysis, or Nyquist Criterion analysis. As always be sure to explain your reasoning carefully.
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