程序代写案例-EEET2387

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RMIT University - EEET2387 Switched Mode Power Supplies Page 1 of 7
EEET2387_2150 - Final Assignment Yingxue Cheng
Due: 11
November 2021 at 9:00AM (AEDT) 3698028
Final Individual Assignment [200 marks available]
Complete ALL questions.
The following is allowed:
• You are allowed to use simulation tools like Powersim PSIM and Mathworks MATLAB
to aid your work.
• You are allowed to use numerical aids like Mathworks MATLAB, GNU Octave, Python,
spreadsheets and Wolfram Alpha to aid you with numerical calculations and approxima-
tions.
• You are allowed to use any calculator.
• You are only allowed to use your individually allocated parameters.
The following is NOT allowed:
• You are not allowed to communicate or discuss with anyone regarding the problems or
the solutions to the problems contained within this assignment.
• You are not allowed to post the problems on any online forum.
• You are not allowed to pay or get another person to prepare your assignment.
• You are not allowed to submit work prepared by another person.
• You are not allowed to copy other people’s work.
• You are not allowed to use parameters other than the individually allocated parameters.
A breach of any of the above may result in disciplinary action in accordance with the University
policies relating to assessment and academic integrity.
Please refer to RMIT’s Academic integrity webpage for further information.
Please refer to RMIT’s How to submit your assessments webpage for further
information. Use the QR-code to submit your Assessment Declaration.
Final Assignment - Copyright RMIT University 2021 Semester 2, 2021
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1. Consider the DC-DC buck/boost converter shown in Fig. 1. The input voltage (Vd) ranges
from a minimum voltage of 7.2 V to a maximum voltage of 13.2 V . A control circuit adjusts
the duty cycle (D) to maintain the output voltage (Vo) at 9 V . The load resistor (Rload) is
36 Ω. The converter operates with a switching frequency (fs) of 71.460 kHz. Assume that
all components are ideal and that the input capacitor (Cd) is large.

Vd Co Rload Vo+
-
id
iD
Io
isw
vsw+ -
L
vD-
+
S
Cd iL
vL
+
-
D
Figure 1: Buck-boost converter.
(a) [10]Calculate the filter inductance (L) to guarantee that the inductor current ripple (∆iL)
is no more than 35% of the average inductor current (IL) for all operating conditions.
(b) [10]Calculate the output capacitance (Co) to guarantee that the output voltage ripple
(∆vo) is no more than 1.5% of the average output voltage (Vo) for all operating con-
ditions. Assume the filter inductance (L) calculated in question 1(a).
(c) [10]Calculate the maximum inductor current (IL,max). Consider all operating conditions.
Assume the filter inductance (L) calculated in question 1(a) and the output capaci-
tance (Co) calculated in question 1(b).
(d) [10]Consider that the input voltage (Vd) is at its maximum (13.2 V ), the output voltage
(Vo) is 9 V , the load resistor (Rload) is 36 Ω, and the filter inductance (L) is as
calculated in question 1(a). Assume that all components are ideal, the input capacitor
(Cd) is large, and the output capacitance (Co) is as calculated in question 1(b). Plot
the waveform for the current flowing through the filter inductor (L), i.e. (iL), over
two switching periods. Clearly indicate the numerical values for the switching period
(Ts), switch ON period (ton), and switch OFF period (toff ). Also, clearly indicate
the numerical values for the maximum inductor current (IL,max), minimum inductor
current (IL,min), average inductor current (IL), and inductor current ripple (∆iL).
Total Marks for Question 1= 40 marks
Final Assignment - Copyright RMIT University 2021 Semester 2, 2021
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2. Consider the flyback converter shown in Fig. 2. The nominal input voltage (Vd) is 340V .
The nominal output voltage (Vo) is 48V . The nominal output load (Rload) is 82Ω. The
converter operates with a switching frequency (fs) of 31.442 kHz. The number of turns
of primary winding (N1) is 340. The input capacitor (Cd) is 100µF and the output ca-
pacitor (Co) is 4.7µF . Assume that all components are ideal (except for the transformer
magnetising inductance Lm) and that losses are negligible.

Vd
Co Rload Vo
+
-
id
im
iD Ioi1
isw
vsw
+
-
Lmv1
+
-
S
D
N1 N2
Cd
Figure 2: Flyback converter.
(a) [8]Specify the number of turns of the transformer secondary winding (N2) that achieves
an output voltage (Vo) of 48V when the input voltage (Vd) is 340V and the duty
cycle (D) is 0.5. Assume that the converter operates in continuous conduction mode
(CCM).
(b) [10]Calculate the transformer magnetising inductance (Lm) that achieves boundary con-
tinuous / discontinuous conduction mode of operation for 80% of nominal output load
(Rload) and duty cycle (D) of 0.5.
(c) [10]Calculate the duty cycle (D) that produces the nominal output voltage (Vo) when the
converter operates with 40% of the nominal output load (Rload).
(d) [12]Calculate the output voltage ripple (∆Vo) when the converter operates with nominal
input voltage (Vd), nominal output voltage (Vo), and 85% of the nominal output load
(Rload). Provide your answer in volts.
Total Marks for Question 2= 40 marks
Final Assignment - Copyright RMIT University 2021 Semester 2, 2021
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3. A transformer for a flyback converter with a full-bridge rectifier front end is required with
the following specifications:
Nominal AC Input Voltage 188 Vrms AC
Minimum AC Input Voltage 127 Vrms AC
Nominal DC Output Voltage 12 V DC
Maximum Output Power Rating 48 W
Switching frequency 95.280 kHz
Converter Efficiency 85%
Table 1: System Parameters
The transformer for this converter is to be designed using a TDK PC47EE50-Z transformer
core with a ferrite grade of PC47 [1]. The details for this core are provided on page 29/44
of the linked datasheet.
Both the primary and secondary windings are to be wound using 0.35 mm diameter enam-
elled copper wire. The boundary between DCM and CCM for the converter is required
to occur at 80% of full load with a duty-cycle of 0.45. The maximum flux density in the
transformer is to be less than 0.2 T.
(a) [5]Calculate the average and peak primary current under full load conditions. Assume
the inductor current is triangular.
(b) [4]Determine the turns ratio Np/Ns required for this flyback transformer.
(c) [2]Calculate the equivalent output load resistance for the converter operating conditions.
(d) [5]Determine a suitable magnetising inductance (Lm) at the CCM/DCM boundary.
(e) [12]If the transformer air gap is given as `air = 0.456 × 10−3 m, calculate the number
of turns required for the primary winding Np if the transformer has a magnetising
inductance of 1.5 mH. [HINT: calculate the total reluctance to determine Np].
(f) [4]The introduction of an air gap into a transformer results in fringing of the magnetic
flux around the air gap. If you had to take this fringing into account for the calculations
of question 3(e), explain briefly how you would adjust your calculations. Why could
we ignore fringing in question 3(e)?
(g) [3]Explain briefly the purpose of adding an air gap to a ferrite material transformer.
(h) [5]Calculate the number of parallel conductors required to keep the average current
density in the primary winding at or below 2 A/mm2 (Jmax). Use the average current
previously calculated in question 3(a).
Total Marks for Question 3= 40 marks
Final Assignment - Copyright RMIT University 2021 Semester 2, 2021
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RMIT University - EEET2387 Switched Mode Power Supplies Page 5 of 7
4. A Texas Instruments UC2842 PWM controller chip [2] is to be used to indirectly control
the output voltage of a 48 W (output rated) flyback-based USB-C charger through peak
current-mode control of the auxiliary output. The flyback converter has a switching fre-
quency of 95.280 kHz. The system parameters are listed in Table 2. The block diagram
of the controller is shown in Figure 3. Refer to the UC2842 datasheet available via the
provided hyperlink for more information.
Vin 85− 265 Vrms AC
Vout 12 V DC
∆Vout 100 mV Vp−p ripple
Iout Maximum 4 A
Vaux 12 V DC
Iaux Maximum 0.1 A
Table 2: System Parameters.
UCx842
UCx843
34 V 5-V
Reference
EN
VREF Good
Logic
Internal
Bias
UVLO
Osc
S
R
PWM
Latch
R 1 V
+
E/A
VCC
GROUND
RT/CT
VFB
COMP
ISENSE
PWM
Comparator
VREF
OUTPUT
VC
PWRGND2R
2.5 V
Copyright © 2016, Texas Instruments Incorporated
11
UC1842, UC2842, UC3842, UC1843, UC2843, UC3843
UC1844, UC2844, UC3844, UC1845, UC2845, UC3845
www.ti.com SLUS223F –APRIL 1997–REVISED APRIL 2020
Product Folder Links: UC1842 UC2842 UC3842 UC1843 UC2843 UC3843 UC1844 UC2844 UC3844 UC1845
UC2845 UC3845
Submit Documentation FeedbackCopyright © 1997–2020, Texas Instruments Incorporated
8 Detailed Description
8.1 Overview
The UCx84x series of control integrated circuits provide the features necessary to implement AC-DC or DC-to-
DC fixed-frequency current-mode control schemes with a minimum number of external components. Protection
circuitry includes undervoltage lockout (UVLO) and current limiting. Internally implemented circuits include a
start-up current of less than 1 mA, a precision reference trimmed for accuracy at the error amplifier input, logic to
ensure latched operation, a pulse-width modulation (PWM) comparator that also provides current-limit control,
and a totem-pole output stage designed to source or sink high-peak current. The output stage, suitable for driving
N-channel MOSFETs, is low when it is in the off-state.
Major differences between members of thes series are the UVLO thresholds, acceptable ambient temperature
range, and maximum duty-cycle. Typical UVLO thresholds of 16 V (ON) and 10 V (OFF) on the UCx842 and
UCx844 devices make them ideally suited to off-line AC-DC applications. The corresponding typical thresholds
for the UCx843 and UCx845 devices are 8.4 V (ON) and 7.6 V (OFF), making them ideal for use with regulated
input voltages used in DC-DC applications. The UCx842 and UCx843 devices operate to duty cycles
approaching 100%. The UCx844 and UCx845 obtain a duty-cycle range of 0% to 50% by the addition of an
internal toggle flip-flop, which blanks the output off every other clock cycle.
The UC184x-series devices are characterized for operation from –55°C to 125°C. UC284x-series devices are
characterized for operation from −40°C to 85°C. The UC384x devices are characterized for operation from 0°C to
70°C.
8.2 Functional Block Diagrams
Figure 11. UCx842 and UCx843 Block Diagram, No Toggle
Figure 3: UC2842 Functional Block Dia-
gram [2].
(a) [5]For the UC2842 block diagram shown in Figure 3, identify the 4 major circuit sections
in this controller that enables current-mode control, and provide a brief description of
their respective functionalities that contribute to a current-mode controller.
(b) Show with a circuit how this controller would be integrated into a flyback converter
system to provide non-isolated regulation of the auxiliary output winding. Your answer
should include fully labelled circuit sketches or schematics that include the following
with standard component values:
i. [7]The oscillator circuit with appropriate standard resistor and capacitor values to
ensure a switching frequency of 95.280 kHz. Ensure that the deadtime, tdeadtime
is less than 7% of the switching period.
ii. [7]The auxiliary voltage feedback measurement and connection to the UC2842 error
amplifier feedback elements. No compensation elements are required.
iii. [7]The VCC supply to the UC2842, i.e. the RC-circuit to limit the charging current
to 3 mA during start-up of the chip’s VCC supply at maximum AC input voltage
of 265 Vrms to avoid exceeding the absolute maximum VCC voltage. The start-up
circuit should be designed so that VCC reaches the typical UVLO turn-on threshold
in 2 s. [HINT: The maximum capacitor voltage during this charge up process may
be considered as 19 V.]
iv. [7]Show with a circuit how you would implement a current sense measurement func-
tion with spike suppression. Assume that the peak primary current is 1.3 A.
(c) [7]The Vishay Siliconix IRFB9N65A Power MOSFET [3] is selected as the primary
switching device for the power supply. Design the gate drive interface between the
UC2842 controller chip and the IRFB9N65A to ensure a turn-on time of less than
0.5% of the switching frequency when the MOSFET is switched with a ±10 V pulse
and a maximum allowed gate current of 0.40 A. Sketch or draw the schematic for this
gate drive circuit interface. [HINT: Use the minimum threshold voltage.]
Total Marks for Question 4= 40 marks
Final Assignment - Copyright RMIT University 2021 Semester 2, 2021
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5. The 12 V main output of a 48 W (rated output) flyback converter is regulated by an iso-
lated feedback circuit based around a TL431 regulator. The auxiliary output is designed
to deliver 12 V at 0.15 A. The general form of this TL431 feedback circuit is shown in Fig-
ure 4. The output of the feedback controller is connected to the Texas Instruments UC2842
regulator chip [2]. Refer to the UC2842 datasheet available via the provided hyperlink for
more information. The current sense amplifier gain Av is provided in the Current Sense
Section of the UC2842 datasheet.
The forward path transfer function of the converter power stage has been analysed experi-
mentally, and the transfer function parameters are listed in Table 3.
Resr = 43 mΩ Co = 2200 µF
Lm = 1.5 mH
Np
Ns
= 10
Dmax = 0.45 Rcs = 0.75 Ω
VF (opto) = 1 V CTR = 1
ILED = 5 mA fs = 95.280 kHz
R22 = 2.49 kΩ R27 = 9.53 kΩ
Table 3: System Parameters.
2.5 V
Point (d)
R22
R27R24C33
TL431
CTR
C32 R26
R19
Point (b) OPTO
R23
Point (a)
Point (c)
Point (e)
Figure 4: Type 2 Compensator using
TL431.
(a) [2]Using the converter parameters provided, calculate the equivalent load resistance Rload.
(b) [10]Determine the overall plant gain Kccm
AvRcs
, as well as ωz, ωp and ωrz for the flyback
converter power stage and provide the open loop transfer function in standard form.
Show all working.
(c) [2]Determine a suitable crossover frequency for the converter. Assume that the secondary
output does not contain an LC-filter.
(d) [4]Determine the open-loop plant gain of the converter power stage |G(ωc)| at the selected
crossover frequency. This gain should include Kccm
AvRcs
.
(e) [14]Select suitable frequencies for the TL431 regulator pole and zero, and accordingly
determine suitable standard component values for the TL431 regulator circuit shown
in Figure 4, given that the required mid-band gain is 8.772.
(f) [8]Using the TL431 compensator design obtained in question 5(e), sketch the compen-
sator Bode magnitude and phase characteristic on semi-log graph paper (available
via Canvas) or using a mathematical tool like Mathworks MATLAB, GNU Octave,
Python or Wolfram Alpha.
Total Marks for Question 5= 40 marks
Final Assignment - Copyright RMIT University 2021 Semester 2, 2021
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References
[1] TDK, “Ferrite for Switching Power Supplies: E cores,” EI/EE/EF/EER/ETD series
datasheet, April 2011. [Online] Available: https://www.jp.tdk.com/tefe02/e141.pdf
[2] Texas Instruments, “UCx84x Current-Mode PWMControllers,” SLUS223F datasheet, April
1997 [Revised April 2020]. [Online] Available: https://www.ti.com/lit/gpn/uc3844
[3] Vishay Siliconix, “Power MOSFET,” IRFB9N65A datasheet, August 2021. [Online] Avail-
able: https://www.vishay.com/docs/91104/91104.pdf
Final Assignment - Copyright RMIT University 2021 Semester 2, 2021

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