2PL2 EE Labs Summer Resits Page 1 of 6 EE Labs Summer 2020 Resits: Coursework (Project) Congratulations! You are now part of the Electronic Engineering teaching team [working as an unpaid intern]. You’ve been given the job of simulating a circuit for a Class-D audio amplifier and turning this into a design for a PCB (Printed Circuit Board) version of the device to be used to teach 2nd- year electronic engineering. To complete this task you’ll need to submit a suitable LTSpice simulation (.asc) & PCB design files (project folder, gerber drill files) with associated documentation by the deadline specified. Your work springs from an existing experiment on the 2PL2 course that sees students building elements of a Class-D audio amplifier on a breadboard. You are part of a team taking this experiment further – all the way to a completed circuit board. The notes for this existing experiment can be found in the KEATS Summer Resits tab. Project Workflow 1. Read through the notes for the existing experiment paying close attention to the expected outputs from the different devices that make up the partial Class-D amplifier build in the notes: 1) astable 555 timer; 2) monostable 555 timer; 3) L293D driver; and 4) output following low-pass filter. Research class-d amplifiers if necessary to gain an understanding of the role of each device in the build. 2. Starting from the LT1160 driver simulation provided, construct a simulation in LTSpice of the complete Class-D amplifier following the illustration provided in LTSpice schematic pdf included in the Summer Resits tab. Demonstrate that you have achieved the correct result by capturing the outputs from: 1) astable 555 timer; 2) monostable 555 timer; 3) LT1160 driver; 4) power MOSFETS; and 5) output following low-pass filter & comparing these to the outputs shown in the existing experiment notes. (Submission: .asc file of your simulation & word document with screenshots of outputs from devices using LTSpice simulation [worth 30% of the project mark]) 3. Starting from the KiCad project folder provided (K1234567_S0003_01), produce a schematic, PCB layout and PCB Design files (gerber and drill) for a circuit board version of the Class-D amplifier. As part of this exercise you will need to: create a schematic symbol for the LT1160 driver, create a footprint for a heatsink & choose appropriate DC-DC converters to provide the different DC voltage supplies needed (Submission: completed project folder as a zipped folder inc. schematic, PCB layout, modified symbol library & gerber and drill files [worth 70% of the project mark]) Photo courtesy Perm State University 2PL2 EE Labs Summer Resits Page 2 of 6 Guide to Completing the LTSpice Schematic If you are not already familiar with LTSpice, read and complete the LTSpice tutorial included in the Summer Resits tab before attempting this exercise. You are provided with LT1160.asc; this is a simulation of the LT1160 driver chip central to the amplifier’s operation with model inputs. You can open this file in LTSpice and run the simulation to study the inputs and outputs with this chip. You can then save the simulation to a new name and use this as the basis for the simulation of the Class-D Amplifier. (Why an LT1160 and not an L293D as in the existing lab? That’s to do with the switching of the power MOSFETs – there must be a delay between switching off one MOSFET and switching on the other; the LT1160 has this delay built in, with no need for additional circuitry; the L293D does not.) Open and study the LT1160 Class-D LTSpice Schematic pdf. This is the complete schematic for the simulation. The elements are: Astable 555 timer with voltage +5V supply (note “+5V” label net as well as 5V voltage level set for supply). We will use this same +5V supply label net to power further devices in the schematic (search “NE555” in devices to bring up the 55 timer symbol – it is in the “misc” folder) This generates 100 kHz sampling pulses (~ 10 µs duration, ~ 0.9µs separation) “AstOut” label net Monostable 555 timer, powered by +5V Inputs: AstOut from astable 555 and Analogue label nets (see below) Output: 555PWM (pulse-width modulation) label net Note: test without Analogue connected (i.e. not connection to CV pin); you will see pulses that turn on for 5 µs, off for 5 µs & turn on when the Astable pulses are low (i.e. in the 0.9µs gaps between the Astable sampling pulses) Circuit elements for adding a 1.74V (approx.) DC offset to the incoming audio signal – this will allow the sampling pulses of the Astable to generate the correct PWM (research PWM to see how reference voltages work) The SINE source is 0.5V (peak) 500 Hz It’s not clear here, but the two protection diodes D2 and D3 are 1N4148 signal diodes 2PL2 EE Labs Summer Resits Page 3 of 6 Inverter (NOT gate) for generating the inverse of 555PWM to drive the lower of the two power MOSFETS (low -> high, high -> low). (see datasheet for the LT1160 driver chip and LT1160 simulation for details.) 24V DC supply for MOSFETS & lowpass filter with 8R2 resistor as load (speaker) The series resistance of the inductor L1 should be set to 7.8 Ohms (this is the series resistance of the inductor you will use in the PCB circuit) Simulation command: 100 ms duration, set to start at 97 ms (thus giving a simulation 3 ms in duration) Complete the Class-D schematic in LTSpice. Run the simulation and capture (separately) screenshots showing 1) without Analogue connected to CV of monostable 555: AstOut PWM InvPWM; and 2) with Analogue connected: output from power MOSFETS before low-pass filter; and reconstructed 500 Hz SINE wave after low-pass filter. Submit .asc simulation and document with the screenshots at the KEATS tab 2PL2 EE Labs Summer Resits Page 4 of 6 Guide to completing KiCad schematic, PCB layout and gerber and drill files If you are not already familiar with KiCad, complete the tutorial in the “Guide to KiCad…” tab on the KEATS page. All the information below, assumes you have completed the tutorial. 1. Download the K1234567_S0003_01 zipped folder from the Summer resits tab on the KEATS page. Unzip & rename replacing K1234567 with your K number 2. Change the names of the following files within the folder, replace 1234567 with your Kings number. K1234567_S0003_01.pro ;Project File 3. Now launch the renamed project file (.pro) 4. Now add symbol project specific libraries in that folder to your project: Select preferences -> Manage Symbol libraries. Select project specific Libraries. Remove any libraries listed. (Select and click the bin icon) Now add K1234567_S0003_01.lib by clicking the “add existing library to table” button. In the Lib_sch folder. The schematics symbol library contains all the schematic symbols you will need to complete the schematic except the symbol for the LT1160 driver chip, which you will have to create – details below 5. Now add footprint project specific libraries in that folder to your project: Select preferences -> Manage Footprint Libraries. Select project specific Libraries. Remove any libraries listed. Now add K1234567_S0003_01.pretty by clicking the “add existing library to table”. (Note .pretty is a folder -- add the folder) The footprint library contains all the footprints you need to complete the PCB layout, except for the footprint for the WA-628-001 heatsink, which you will create. 6. Now attach the page layout description File: Open the schematic editor from the project manager From the menu bar select file -> page settings. Click Browse in the Title Block parameters window and point to the KCL_Template.kicad_wks file in the template folder in the project folder. 7. Enter all the requested information. (Note: You can click the Export to other sheets checkbox to copy to the PCB file template) 8. Open the K1234567_S0003_01 Schematic pdf in the project folder. This is the complete schematic. Note that now that we are moving to an actual device there are some differences to this schematic compared to the LTSPice simulation a. Input and Output of Audio is via stereo jacks (in a mono configuration). b. The +24V from an external supply is introduced to the board via a barrel jack 2PL2 EE Labs Summer Resits Page 5 of 6 c. The +12V to power the LT1160 and +5V to power the 555 timers and the 7404 NOT (inverter) IC are derived from the +24V supply using two DC-DC converters d. The 1.74V DC offset voltage for the analogue in signal is derived from the +5V via an LM317 voltage regulator. e. Several of the resistors have been replaced with potentiometers to allow for the fine-tuning of the sample-pulse frequency, the PWM on/off time and the 1.74V DC Offset f. To facilitate the above, test points have been added to make monitoring of signals at different points in the circuit easier. g. The 7404 is here in a single-gate package, the 74LVC1G04 chip, not the more usual Hex gate 74LS04 chip 9. Creating the LT1160 symbol Consult the notes for creating schematic symbols contained within the tutorial in the “Guide to KiCad…” tab. Open the symbol editor and select “create new symbol”. It is recommended that the grid be set to 50 mils. Create the symbol as shown left. Pay close attention to the numbering of the pins, and to their designation (input, output or not connected). Once you have created the symbol save it to the Kxxxxxxx_S0003_01 symbol library. 10. Complete the schematic as according to the pdf. Run an electrical rule check (ERC), correct any errors. 11. The MOSFETs and LM317 will generate a lot of heat; this can be dissipated with a heatsink. The heatsink for the LM317 slips on over the LM317, so does not need take up more space on the board. However, the heatsink for the MOSFETS needs to be accommodated on the board. Thus a footprint needs to be created for it. This can be a simple rectangle on the F.SilkS layer with dimensions appropriate to the heatsink. Open the WA627 WA628 datasheet in the datasheets folder and find the dimensions for the WA 628-001 heatsink. Create a footprint for this called “TO-220 Heatsink” using the footprint editor and save this to the project footprints folder. 12. Assign footprints to the components. All the footprints required are contained within the .pretty library in the project folder. Note: a. The footprint for the IRFZ44N MOSFETS is TO-220-3_Vertical b. For the LM317 is TO-92_Inline_Wide c. For the 74LVC1G04 is TSOP-5 d. For the other ICs, pay attention to the number of pins 13. Save the netlist. 2PL2 EE Labs Summer Resits Page 6 of 6 14. Return to the project manager. Open the PCB editor. Edit the page settings in line with the page settings of the Schematic. In the board set-up create a new net class for +24V. Set the trackwidth for this class as 0.6 mm. Assign the new net class to the +24V net. The default class track width should be set as 0.25 mm and used for all other nets 15. On the edge cuts layer create a board outline of 150 mm x 75 mm 16. On the margin layer create a keep-out of 1mm thickness along the edge of the board 17. Return to the schematic and tools > update PCB from schematic 18. Notes for completing the PCB layout: a. Create a ground fill on the B.CU layer covering the whole board. b. All GND nets of surface-mount components should be connected to GND using VIAS. The example left shows the two surface-mount protection diodes with ground VIAS. (information on vias can be found in the tutorial and online.) c. Create a fill on the F.CU layer for the +5V net. This needs to cover only those parts of the board where the components needing +5V are located – place your components to maximise the efficiency of this fill; for example, see right. d. Note: once you have created the fills, you will find it useful to use the “do not show filled areas in zones” button on the left toolbar to hide the planes for ease of placing tracks. e. Complete the placing of components and making of tracks on the F.CU layer. f. Use the add text function to add to the F.SilkS layer you K number and the title of the build (Class-D Audio Amplifier) and any useful annotation (e.g. what each testpoint monitors, which stereo jack is for Audio In, which for Audio Out; that the input voltage is +24V DC). g. Once you have completed the layout run the design rule check (DRC), correct any errors. h. Use the 3D viewer to check the look of your board. Note that some components will not appear as there is no 3D model for them. i. Generate the gerber and drill files. Zip the project folder and submit the entire zipped folder using the link on the KEATS module page.
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