ICS 51: Introduction to Computer Organization
Sample problems #5 Solutions on Spring 2021
1. [MIPS Processor Architecture] What is the range of addresses to which beq
instruction can branch in MIPS?
(Note: when you say 2Kbytes, remember that “K” = 210= 1024).

The instruction word for beq instruction is:


Fill up the following statement:
beq can branch to instructions (1)________bytes before the branch to instructions
(2)________bytes after the branch instruction.



















2. [MIPS Microarchitecture] Based on the MIPS architecture and control tables
below, answer the following questions:








a. Fill the control bits for each instruction in the table below. If a control bit is not
important, put x in its field. The MemWrite control bit for memory is set to 1 when
the memory is in the write mode and it is set to 0 when the memory is in the read
mode.



b. Suppose that the following control signals are not working correctly:
 ALUControl[0] is always 1.
 ALUSrc is always 1.
Which of these instructions are affected and will malfunction by these faulty control
signals? Briefly explain why.
add, slt, beq, addi, lw, sw


Answer:
add, slt, beq, addi, lw, sw

For add, slt, beq: since the ALU src is always 1, we can't compare RD1 and RD2 from
the register file to ALU.

For addi, lw, sw, we cannot add because ALU control[0] is always one.


3. [ALU Design]
a. Design a 4-bit ALU using multiplexers, logic gates, and AT MOST ONE 4-bit
adder to determine the value out in the following table.







b. Add overflow detection to a 4-bit adder.




c. Add overflow detection to the ALU by using ALU function inputs F[2:0] and
the adder’s overflow signal.
Assume your 4-bit adder has a 1-bit output signal, OV_add, for overflow detection
already, like Q3-b.
1. Provide the truth table for ALU overflow. (Input: OV_add, F[2:0]. Output:
OV_alu)
2. Add the OV_alu circuit for ALU overflow using logic gates. (You can draw
the used/related circuit only.)




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