EE20084: Structured Programming Coursework
S. R. Pennock & J. Graham-Harper-Cater
February 17, 2021
1 Introduction
This programming coursework is designed to allow you to develop your structured program-
ming skills in the context of an engineering problem using Python. The main objective of the
coursework is to write a program that should analyse an electrical circuit, as described below.
There are a number of extensions possible to the main objective that will allow you to gain
additional marks. There is an all day laboratory session where the main aim is producing a
Design Report on what is to be implemented, and one and a half days laboratory session
where you should implement, debug and test the code. You are, of course, free to develop
and test the code in your own time. Automated tests will be used on your submission to as-
sess a mark and so it is critically important that you ensure that your code complies with
the syntax and file formats described in this document.
2 The Objective
Your objective is to write a program that analyses cascade circuits, such as shown in Fig-
ure 2.1, where series and shunt resistances of any value can be connected in any order
between a source and a load. This is exactly the same problem that underpins expensive
circuit analysis software. For these circuits the ABCD matrix analysis scheme outlined in the
Appendix is a natural, and simple, way to analyse the circuit.
Figure 2.1: A cascade circuit of series and shunt resistances. Node numbers, 1 to 6 in this
case, are used to define how components are connected. Node zero is the common (ground?)
connection.
1
EE20084: Structured Programming Coursework
Your program must perform the following tasks:
1. Read in the circuit input file using the format specified below.
2. Analyse the circuit to evaluate the requested output variables.
3. Write the output variables to a file in the specified format.
You may extend the work in any way that you wish, so long as it is obvious and does not
interfere with completion of the automated tests. For example your program may display a
representation of the circuit under analysis. Your program should display a message that
explains any such extensions you chose to make.
3 Running the program
The program is to read an input data file, say ’test.net’, and output to a results file, say ’test.csv’.
These files are to be specified in the command line, so to run ’MyCode.py’ on these files the
command line should be
python MyCode.py test.net test.csv
4 Input and Output file formats and syntax
The files that describe the circuit (the input) and the results (the output) are described here.
Your program should be as tolerant as possible of format errors in the input files and as precise
as possible in the format of the output files. Note that because an automated tester will be
used to assess your output files you must comply exactly with the file format described here.
4.1 Input file
The input file contains a description of the circuit that is to be analysed. Lines that start with
the hash symbol (#) are comments. The input file will contain three blocks, each of which is
described in greater detail below:
CIRCUIT block: This is delimited by and . It defines the compo-
nents in the circuit and how they are connected to each other.
TERMS block: This is delimited by and . It defines the source and
the load.
OUTPUT block: This is delimited by

and

. It defines the output
filename to use, the variables to be printed out into the file and the units to be used for
each variable.
The following example is available on the Moodle site as ‘a_Test_Circuit_1.net’.
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EE20084: Structured Programming Coursework
4.1.1 CIRCUIT block
The start of the CIRCUIT block is indicated by the xml style text and the end by
. Each resistor component in the circuit is defined by two node numbers, one for
each end of the component, and either its resistance, R, or its conductance G=1/R.
# define a circuit between and delimiters
# Elements have two node numbers and either a
# resistance R=1/G Ohms or a conductance G=1/R Seimens.

n1=1 n2=2 R=47
n1=2 n2=0 R=100
n1=2 n2=3 R=150
n1=3 n2=4 R=330
n1=4 n2=0 G=0.0125
n1=4 n2=0 R=82
n1=4 n2=5 R=25
n1=5 n2=0 R=280
# components do not have to follow their order in the circuit
n1=6 n2=0 R=100
n1=5 n2=6 G=0.02

Note that components do not have to be specified in the order that they appear in the circuit,
the node numbers show how the components are connected.
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4.1.2 TERMS block
The TERMS block defines the source and the load attached to the circuit.
The source is implicitly connected between
node 0, the common node, and node 1.
The source may be given as a Thevenin
source or a Norton source.
The load is connected between the implicit
node 0 and the last node specified in the CIR-
CUIT block. Figure 4.1: Thevenin and Norton sources.
Equivalent when VS = IS RS.
# define the terminations between and delimiters

# a 5V Thevenin voltage source with RS=50 ohms connected
# between node 1 and the implicit common (0) node
VT=5 RS=50
# or a 2.5 Amp Norton current source with RS=25 Ohms
#IN=2.5 RS=25
#IN=2.5 GS=0.04
# load connected between last node (6 in this case) and the implicit common (0)
RL=75
Fstart=10.0 Fend=10e+6 Nfreqs=10
# Frequency start, end and number of frequencies

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4.1.3 OUTPUT block
The OUTPUT block defines the desired output of the circuit analysis, including a filename
where the output variables will be written. It defines which variables are to be written, in what
order, and the units to be written for each variable. The variables to be output can be:
• Vin - Input Voltage
• Iin - Input Current
• Pin - Input Power
• Zin - Input Impedance
• Vout - Output Voltage
• Iout - Output Current
• Pout - Output Power
• Zout - Output Impedance
• Av - Voltage Gain
• Ai - Current Gain
Note: input values are defined as being measured between nodes 0 and 1 (through node 1
for current). Output values are defined as being measured between the node 0 and the load
node, which is the last node that is defined in the CIRCUIT block of the input file.
# define the outputs between

and

delimiters
# each line has a parameter and its units if there are any.

Vin V
Vout V
Iin A
Iout A
Pin W
Zout Ohms
Pout W
Zin Ohms
Av
Ai

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4.1.4 Output file format
The first line of the output file should be the variable type. The second line of the output file
should be the units for the output variables and the third and subsequent lines are the variable
values. Apart from the frequency the output values are all complex numbers in either real and
imaginary format, or when using decibel outputs in magnitude and phase. The commas
following the labels and the data should all align. The units for a linear gains should be L.
The following output results from the example input file ‘a_Test_Circuit_1.net’. The circuit only
contains just resistors, so the output is the same at all frequencies:
Freq, Re(Vin), Im(Vin), Re(Vout), Im(Vout), Re(Iin), Im(Iin), Re(Iout), Im(Iout), Re(Pin), Im(Pin), Re(Zout), Im(Zout), Re(Pout), Im(Pout), Re(Zin), Im(Zin), Re(Av), Im(Av), Re(Ai), Im(Ai)
Hz, V, V, V, V, A, A, A, A, W, W, Ohms, Ohms, W, W, Ohms, Ohms, L, L, L, L
1.000e+01, 3.615e+00, 0.000e+00, 4.387e-02, 0.000e+00, 2.769e-02, 0.000e+00, 5.849e-04, 0.000e+00, 1.001e-01, 0.000e+00, 5.029e+01, 0.000e+00, 2.566e-05, 0.000e+00, 1.306e+02, 0.000e+00, 1.213e-02, 0.000e+00, 2.112e-02, 0.000e+00
1.111e+06, 3.615e+00, 0.000e+00, 4.387e-02, 0.000e+00, 2.769e-02, 0.000e+00, 5.849e-04, 0.000e+00, 1.001e-01, 0.000e+00, 5.029e+01, 0.000e+00, 2.566e-05, 0.000e+00, 1.306e+02, 0.000e+00, 1.213e-02, 0.000e+00, 2.112e-02, 0.000e+00
2.222e+06, 3.615e+00, 0.000e+00, 4.387e-02, 0.000e+00, 2.769e-02, 0.000e+00, 5.849e-04, 0.000e+00, 1.001e-01, 0.000e+00, 5.029e+01, 0.000e+00, 2.566e-05, 0.000e+00, 1.306e+02, 0.000e+00, 1.213e-02, 0.000e+00, 2.112e-02, 0.000e+00
.
.
.
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5 Additional extension features
The following additional extension features can be added in order to gain more marks.
5.1 Exponent prefixes
Add the exponent prefixes (p, n, u, m, k, M, G) and use them in reading and writing all input
and output variables.
Symbol Prefix Factor
p pico 10−12
n nano 10−9
u micro (µ) 10−6
m milli 10−3
k kilo 103
M mega 106
G giga 109
Decibels and phase
Add the ability to express the outputs in decibels. The

block would be of the
form:

Vin dBV
Vout dBV
Iin dBA
Iout A
Pin dBW
Zout Ohms
Pout W
Zin Ohms
Av dB
Ai

The output should be decibels and the argument or phase in radians of the complex value.
The separator between the magnitude in dB and the phase should be /_, i.e. a slash and an
underscore. Example output is:
Freq, |Vin|, /_Vin, |Vout|, /_Vout, |Iin|, /_Iin, Re(Iout), Im(Iout), |Pin|, /_Pin, Re(Zout), Im(Zout), Re(Pout), Im(Pout), Re(Zin), Im(Zin), |Av|, /_Av, Re(Ai), Im(Ai)
Hz, dBV, rads, dBV, rads, dBA, rads, A, A, dBW, rads, Ohms, Ohms, W, W, Ohms, Ohms, dB, rads, L, L
1.000e+01, 1.116e+01, 0.000e+00, -2.716e+01, 0.000e+00, -3.115e+01, 0.000e+00, 5.849e-04, 0.000e+00, -1.999e+01, 0.000e+00, 5.029e+01, 0.000e+00, 2.566e-05, 0.000e+00, 1.306e+02, 0.000e+00, -3.832e+01, 0.000e+00, 2.112e-02, 0.000e+00
1.111e+06, 1.116e+01, 0.000e+00, -2.716e+01, 0.000e+00, -3.115e+01, 0.000e+00, 5.849e-04, 0.000e+00, -1.999e+01, 0.000e+00, 5.029e+01, 0.000e+00, 2.566e-05, 0.000e+00, 1.306e+02, 0.000e+00, -3.832e+01, 0.000e+00, 2.112e-02, 0.000e+00
2.222e+06, 1.116e+01, 0.000e+00, -2.716e+01, 0.000e+00, -3.115e+01, 0.000e+00, 5.849e-04, 0.000e+00, -1.999e+01, 0.000e+00, 5.029e+01, 0.000e+00, 2.566e-05, 0.000e+00, 1.306e+02, 0.000e+00, -3.832e+01, 0.000e+00, 2.112e-02, 0.000e+00
.
.
.
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EE20084: Structured Programming Coursework
Logarithmic frequency sweep
Add the ability to calculate at logarithmically spaced frequencies as specified in the
block as
LFstart=10.0 LFend=10e+6 Nfreqs=50
The 10 values of log(f) are then evenly spaced, but linear frequencies are to be output.
Output time response
Add the ability to calculate the time response h(t) from the frequency response H(ω)
h(t) = IFFT (H(ω))
where H(ω) is any of the output parameters.
The command line should be modified to be:
python MyCode.py -i test -t M
where M is zero or a positive integer. The output is in the file ’test.csv’ resulting from the input
file ’test.net’. In the output file ’FREQ’ and ’Hz’ should be replaced by ’TIME’ and ’Sec’. The
value of M denotes the multiplication of the length of the IFFT calculation. The number of
points in the IFFT calculation should be multiplied by 2M , with the additional frequency data
all set to zero. This zero padding will produce a more detailed output as a function of time as
the sample points are more closely spaced in time.
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EE20084: Structured Programming Coursework
6 Workplan
6.1 LOIL and IPT Sessions
There are LOIL and IPT sessions on the timetable. In the earlier weeks of the semester these
are directed towards stand alone tasks that are designed to help you understand particular
parts of the lecture course. These tasks are available to you on the Moodle site. The later
sessions in weeks 9, 10 and 11 are left for discussions on particular issues that you may need
to raise while you do exploratory work on your analysis program.
6.2 First Laboratory session, week 5
During the first all-day laboratory session you should develop your Design Document, and
attempt to create the basic I/O framework for your program. At the end of this session you
should have the majority of the Design Document and a program that is reads in the input file
and writes out test data correctly. You should include in your program a dummy analysis that
produces a dummy solution for output.
6.3 Second Laboratory session, week 10 and 11
In the second laboratory session you should try to implement the analysis program itself and
record all the needed test data. You can also work in your own time, as all campus computers
will have Visual Studio or Anaconda/Spyder installed.
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EE20084: Structured Programming Coursework
7 Assessment
There are three assessments for the coursework in this unit, and the Marking Rubric that will
be used can be seen on the Moodle site:
Design Document: The design document for your circuit analysis program should be sub-
mitted via Moodle by 4pm on March 12th 2021. It should not include blocks of Python
code, but it should include:
• Analysis of the problem so that your program will analyse any circuit defined in the
input file format, the outline code structure you are proposing in terms of functions
or functional blocks and the data flow through them. Flowcharts can be a simple
tool to describe the structure and flow of the program.
• A description of every function or functional block you plan to implement as a part
of your program, and how each one is to be tested.
• A description of every data structure, array and enumerated variable you plan to
implement as a part of your analysis program.
Typically the design can be expressed in 3 or 4 pages. 20% of the coursework mark
(10% of the Unit mark) will be awarded for this.
Circuit analysis program - Code: Your circuit analysis Python program that is executable
within the automated test mark. This is due in via Moodle by 4pm on April 30th 2021.
You will need to submit your Python files which are executable in a single directory or
folder, as needed by the auto tester. Do NOT submit your whole project directory (marks
will be deducted if you do this).
Your submitted executable will run through a set of automated tests, and the results
will form part of your marks. Make sure that your program runs as expected on the
computers in the undergraduate labs. Source code will be inspected for good read-
ability, commenting and coding standards according to the EE20084 coding standards
document (available on Moodle).
40% of the coursework marks (20% of the Unit marks) will be awarded for this.
Circuit analysis program - Final Report: This should be should be submitted via Moodle
by 4pm on April 30th 2021. The report should cover the description of how the finished
code operates, documentation of the code, the testing strategy and test records used on
components of the code, and the testing strategy and test records used on the complete
code.
40% of the coursework marks (20% of the Unit marks) will be awarded for this.
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EE20084: Structured Programming Coursework
8 Opportunities for feedback
Various opportunities for feedback exist during the unit. There are tutorial sessions and lab-
oratory sessions where you can gain feedback from lecturers and demonstrators. In addition
the will be feedback on the design document that you submit via Moodle.
Labs/tutorials: At the end of the lab/tutorial session, consider whether you have success-
fully completed the tasks for that session or not:
Struggling: “The code didn’t work and I don’t know why”
Basic: “The code compiled and sort of worked”.
Advanced: “ I was able to spot out algorithmic and syntax errors before compilation. I tested
the code in detail and it always works the way that it should”.
Software: We will provide feedback on software submitted.
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EE20084: Structured Programming Coursework
A ABCD or Chain Matrix Analysis
The ABCD matrix relates voltages and currents at the input and output connection ports of a
circuit. The ABCD matrix is also known as the chain matrix or voltage transmission matrix.
The ABCD matrix formulation is particularly useful for the cascade connection of components,
which is a very common and natural way for components to be connected.
Figure A.1: Cascade of three 2-port circuits.
Figure A.1 shows three components connected in cascade. The ABCD matrix of the whole
circuit is simply found by multiplying the ABCD matrices of the elements in the order that they
appear in the circuit:
[
A B
C D
]
=
[
A1 B1
C1 D1
] [
A2 B2
C2 D2
] [
A3 B3
C3 D3
]
(1)
A.1 Definition of the ABCD matrix
Consider a linear two-port circuit with voltages V1 and V2 and currents I1 and I2 at the two
ports.
V1 = AV2 + BI2
I1 = CV2 + DI2
The equation set is cast into the ABCD matrix form as
[
V1
I1
]
=
[
A B
C D
] [
V2
I2
]
= [T ]
[
V2
I2
]
(2)
This can be simply inverted to find:
[
V2
I2
]
= [T ]−1
[
V1
I1
]
= 1
AD − BC
[
D −B
−C A
] [
V1
I1
]
(3)
The four parameters of the matrix can be determined by examination of the circuit with
open and short circuit load conditions.
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A.2 Examples of ABCD Matrices
Series Impedance
In the case of a series impedance, Z = 1/Y ,
the ABCD matrix is:[
A B
C D
]
=
[
1 Z
0 1
]
(4)
Shunt Admittance
In the case where the shunt element is an
admittance Ysh = 1/Zsh:[
A B
C D
]
=
[
1 0
Ysh 1
]
(5)
A.3 Cascade of several circuit elements
The cascade connection is a very common way of connecting components. Consider the
case where there are several two-port circuits in cascade.
Figure A.2: Cascade of three 2-port circuits.
The behaviour of the overall circuit is determined by the ABCD matrices of the elements of
the cascade:
[
V1
I1
]
=
[
A1 B1
C1 D1
] [
V2
I2
]
= [T1]
[
V2
I2
]
[
V2
I2
]
=
[
A2 B2
C2 D2
] [
V3
I3
]
= [T2]
[
V3
I3
]
[
V3
I3
]
=
[
A3 B3
C3 D3
] [
V4
I4
]
= [T3]
[
V4
I4
]
(6)
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EE20084: Structured Programming Coursework
Relating the voltages and currents from left to right:[
V1
I1
]
= [T1]
[
V2
I2
]
= [T1] [T2]
[
V3
I3
]
= [T1] [T2] [T3]
[
V4
I4
]
=
[
An Bn
Cn Dn
] [
V4
I4
]
(7)
So the ABCD matrix of the cascade network is determined by multiplying together the ABCD
matrices of the elements in the order they appear in the cascade circuit. This is why the matrix
is sometimes referred to as the chain or voltage transmission matrix.
Observation
For a general cascade circuit the overall ABCD matrix is simply the multiple of the
ABCD matrices of the individual components of the cascade, in the order that they
occur in the cascade:
[Tn] = [T1] [T2] [T3] . . . [TM ] (8)
From the ABCD matrix of the complete cascade network various features of the complete
network are easily found, such as input impedance, voltage gain, current gain, power gain.....
A.4 Input and output impedance
When a load, ZL, is connected at the end of the cascade V4I4 = ZL and the input impedance
as seen by the source, Zin is
Zin =
V1
I1
= AnV4 + BnI4
CnV4 + DnI4
=
An
V4
I4
+ Bn
Cn
V4
I4
+ Dn
= AnZL + Bn
CnZL + Dn
(9)
When a source, ZS, is connected the output impedance as seen at the load end, Zout is
Zout =
DnZS + Bn
CnZS + An
(10)
A.5 Voltage, current and power gain
As V4
I4
= ZL = 1YL using the base definition of the ABCD matrix:
V1 = AnV4 + BnI4 = AnV4 + BnV4YL (11)
the voltage gain is:
AV =
V4
V1
= 1
An + BnYL
(12)
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EE20084: Structured Programming Coursework
Likewise
I1 = CnV4 + DnI4 = CnI4ZL + DnI4 (13)
and the current gain is:
AI =
I4
I1
= 1
CnZL + Dn
(14)
The power gain is:
AP = AVA∗I (15)
where the complex conjugate of the current gain is needed.
A.6 Transmittance
The transmittance from source to load is:
T = 2
AnZL + Bn + CnZLZS + DnZS
(16)
A.7 Familiarisation Exercises
It is often easier to develop functions or programs to implement an algorithm if you can perform
the operations yourself ’by-hand’. Examples that you are convinced are correct often (always?)
form test cases for you to prove your software programs against.
These familiarisation exercises illustrate the basic steps that are needed to perform an
ABCD matrix circuit analysis.
Example 1
Figure A.3: A two element cascade circuit of
series and shunt resistances.
Question 1
In the case where ZS = R1 = R2 =
ZL = 50Ω calculate the ABCD matrix,
Zin and Av.
Question 2
In the case where ZS = ZL = 50Ω and R1 = R2 = 150Ω calculate the ABCD matrix,
Zin and Av.
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EE20084: Structured Programming Coursework
Question 3
In the case where ZS = ZL = 50Ω, R1 = R2 = 150Ω and Vs = 5 V olts calculate
V1, I1, V2 and IL.
Example 2
Figure A.4: A two element cascade circuit of
shunt and series resistances.
Question 4
In the case where ZS = R1 = R2 =
ZL = 50Ω calculate the ABCD matrix,
Zin and Av.
Question 5
In the case where ZS = ZL = 50Ω and R1 = R2 = 150Ω calculate the ABCD matrix,
Zin and Av.
Question 6
In the case where ZS = ZL = 50Ω, R1 = R2 = 150Ω and Vs = 5 V olts calculate
V1, I1, V2 and IL.
S. R. Pennock & J. Graham-Harper-Cater Page 16 February 17, 2021

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