5CCS2PL2 Timing

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5CCS2PL2 Sampling II: Sampling Timing (Relaxation Oscillator and
Monostable)
Expected time to complete: 120 – 140 minutes



In this Lab You Will:
• learn the principles behind the design and building of practical sampling timing
circuits from logic gates

REMEMBER TO FRITZ ALL LAYOUTS AND UPLOAD BEFORE ATTEMPTING
THE LAB

Deliverables Checklist (details given in notes)
1. LTSpice Schematics and Screenshots of Simulation results according to the
simulation section
2. Photos of Handwritten notes, paying attention, but not restricting yourself, to
the requirements specified in the notes below, remembering to compare and
contrast results
3. Screenshots of M2K results for all builds
4. Short (≤ 10 seconds) unedited video of the monostable panning from the
build to the output on the SCOPY oscilloscope screen

Equipment
ADALM2000
Breadboard
Wires
4011BE Quad 2-Input NAND gate
40106BE Quad 2-Input Schmitt NAND
gate
74LS00
Red 5mm LED
Momentary Switch

470Ω Resistor
10kΩ Resistor
22kΩ Resistor
68nF Capacitor
10μF Electroyltic Capacitor

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Background
As was seen in the sampling and reconstruction, lab, a key feature of sampling is the
sampling pulses. In this lab we will look at two different approaches to generating
sampling pulses in practical circuits using logic gates.
RELAXATION OSCILLATOR

The figure left shows the construction of a relaxation
oscillator. It is built from a 40106BE Schmitt trigger
inverter with typical switching thresholds of 1.9V and
2.9V. An RC network connects the output to the input,
and this feedback causes the output to continually
change state at a rate fixed by the values of R and C.
In order to analyse the behaviour of the circuit, we will
assume that the power supply has just been connected
(time = 0). The capacitor will be completely discharged,
so Vin will start off at 0V. Since the Schmitt
trigger has an inverted output, the initial value
of Vout will be 5V. There will therefore be a
voltage of 5V across the 10kW resistor, so
current will flow through it and Vin will slowly
rise as the capacitor charges up. Eventually
Vin will reach the 0/1 threshold of 2.9V,
causing Vout (the inverted output) to drop from
5V to 0V. Current will now flow through the
10kW resistor in the opposite direction
discharging the capacitor, and Vin will slowly
fall towards the 1/0 threshold of 1.9V. Once it
gets there, Vout will of course change state to 5V and the capacitor will start to
charge up again. This cycle will continue with Vout regularly changing state.
We can calculate how fast the system oscillates by using a formula which gives the
relationship between the voltage across the resistor and time for an RC network;
V = V e
V is the voltage across the resistor at time t (seconds), V is the voltage when t = 0.
The value of e is about 2.71 and its position in the formula produces the required
exponential function, R and C are the values of the resistor and capacitor in ohms
and farads. Manipulating the formula and taking logs gives a much more useful
version;
t = RC log (V /V)
which we can now apply to our circuit. If we assume that Vout has just changed
state to 5V, Vin will be 1.9V. If we also assume that negligible current is taken by the
Schmitt trigger, it should be clear that we are dealing with a standard RC network.
One end is held at 5V, the other at 0V, with an initial voltage of 1.9V in the middle.
Looking at the voltage values across the resistor to input to the formula;
0
-( / )t RC
0
e
e 0
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V = 5 - 1.9 = 3.1V, and the capacitor will continue to charge until
V = 5 - 2.9 = 2.1V

t = RC log (V /V)
t = (10 x 10 ) x (100 x 10 ) x log (3.1/2.1)
t = 0.39ms
This means that Vout stays at 5V for 0.39ms. We can perform a similar calculation
to determine how long Vout remains at 0V. Referring to figure 1, Vin starts off at
2.9V and slowly falls to 1.9V. The values of V and V will be 2.9V and 1.9V,
respectively. If these are substituted into the formula for t, we obtain t = 0.42ms.
This sort of output is known as a square wave. The output is at 5V for 0.39ms, and
at 0V for 0.42ms. Each cycle of the signal therefore takes place in a time of 0.81ms;
which is called the period of the waveform. It is more usual to specify the frequency
of the waveform i.e. the number of cycles it goes through in one second. Frequency
and period are linked by the formula;

f = 1/T

where f is the frequency of the waveform
T is the period of the waveform

The units for f and T are Hertz and seconds. So the frequency of this oscillator is
1/(0.81 x 10 ) = 1.23 kHz.

The circuit we have been looking at is an example of a relaxation oscillator. This
oscillator is a sure-start system, that is it has to oscillate and will do so automatically
when switched on. Furthermore its frequency is predictable, depending on the
switching thresholds of the Schmitt trigger, and the values of the capacitor and
resistor.


0
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3 -9
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0
-3
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THE MONOSTABLE
A monostable is a device which produces a single pulse when it is triggered.
If you look at the figure left, you will see that
by briefly pulling down the input pin to
logic 0, the two outputs of the system
change state for a finite time.
A monostable has one stable state in which it will remain quite happily, and another
state that it will only stay in for a finite time.
When the system has been triggered it enters its temporary state, stays there for a
while, and then returns to its permanent state to await the next triggering. Every time
that falls from logic 1 to logic 0, the monostable is triggered, and pushes Q up to
logic 1. Q will stay there for a fixed length of time, regardless of the state of (once
you have triggered the system it ignores its input). Q is then returned to logic 0, and
the system is ready to be triggered again.
The triangle at the input of the monostable indicates that it is triggered by a logic
transition, and the circle (indicating an inversion), that this transition will be from logic
1 to logic 0. The monostable in the figure can therefore be described as negative-
edge triggered with complementary outputs.
A monostable made from CMOS NAND gates is
shown right, and its operation is illustrated by the
four waveforms.
Starting off with at logic 1, will be logic 1 as
Vout is pulled down to 0V by the resistor R.
When a falling edge is fed into it goes from
logic 1 to logic 0, Vin rises to 5V and Vout is
pulled up with it. So falls to logic 0. Since a
logic 0 at either input of a NAND gate will hold its
output at logic 1, the feedback path ensures that
Vin will remain at 5V until goes back to logic 1.
So can be raised back to logic 1 at any time
without affecting the fall of Vout to the 0V rail.
Once Vout gets down to 2.5V, will rise to logic
1. If is also logic 1 this forces Vin down from
5v to 0V as both inputs of the NAND gate are
logic 1. Vout is then pushed down below the
ground supply rail and clamped by the protection
diode in the NOT gate. Provided that the triggering pulse is shorter than the output
pulse, the system works very well. Once triggered it ignores the state of its input,
and the output pulse is well defined and free from glitches.
The output pulse width can be determined using the formula t = RC log (V /V).
A monostable made from CMOS gates with an actual switching point of 2.5V (as
illustrated in the figure) would give a pulse width of RC log (5/2.5), which would be
0.7RC.
T
T
T
T
T Q
T
Q
Q
T
Q
T
e 0
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Procedure

Simulation
Relaxation Oscillator
The circuit is very straightforward; the Schmitt
trigger is the “schmittinv” device found in the
“digital” folder. Note that there is no connection
to the connector at the bottom left corner of the
Schmitt. Before running the simulation, we
need to set-up the generic Schmitt trigger to
behave in something approximating the same
way as
the
40160BE Schmitt trigger. Right-click on the
symbol to bring up the attributes window and
enter the values shown right to both the
spiceline and spiceline2.
1. Run the simulation, monitor the input and output from the trigger, screenshot
and upload along with the .asc file.
Monostable
Simulating the
Monostable is also
quite straightforward,
drawing, as it does,
on methods you
have employed with
other simulations –
so, here, we are
once again using a
voltage-controlled
switch to simulate a
push-button switch. Note that a .model must be added for the switch using a spice
directive – consult the notes for the sampling and reconstruction lab for how to do
this (we can use the same parameter values as those we used for the CD4066 in the
sampling simulation). The switch is controlled with a voltage supply (V2 here) set to
PULSE, with 0V start voltage, 5V on voltage, a delay of 20ms before switching on, a
200ms period and 1 cycle (the latter two parameters simply allow us to send one
pulse for the duration of the simulation).
The NAND gate is the “and” symbol in the Digital folder. The AND device in
LTSpice has a multitude of inputs, but all but two (any two) can be ignored. To
operate in “NAND” mode, we simply select the connector attached to the “o” on the
output side of the symbol. The AND/NAND defaults to having a “HIGH” voltage of
1V. As this does not affect the simulation, we could leave this, but is it easy to
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change – right-click on the symbol
and change the spiceline to
include Vhigh=5 Vlow=0 as
shown right. Remember to do
this for all three NAND gates.
1. Run the simulation,
monitor Q (output of NAND
A3 above) and the input to NAND A2, screenshot and upload this to the folder
along with the .asc file.
Note (additional, optional): there is no model for the CD4011 in the standard
LTSpice build, but, if you are interested, you can add a third-party model and centre
you simulation on that. Google “CD4000.lib” and follow the instructions for adding
this library to spice and including it in a simulation schematic. This has the
advantage of using a standard two-input NAND symbol; it’s just that the process of
generating the simulation is more involved for, essentially, the same result.




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Experiments
Note: the relaxation oscillator is quite a quick build; you will need to spend
more time on the monostable – factor this into the time you allocate to the
experiment.
Circuit 1: Relaxation Oscillator
1. Build the circuit shown
left – note that the 40106 is a
multi-unit device in KiCad, so
both U18A and U18G here
are part of the same single
40106 IC; pay attention to the
pin numbers, as always.
2. Set V+ to 5V and
enable.
3. Adjust the timebase
and amplitude of the two
oscilloscope channels as
required.
4. If all is well the circuit will be
oscillating, and you should be able to
observe the values of the threshold
voltages VT+ (positive trigger
threshold) and VT- (negative trigger
threshold) on CH1 of the oscilloscope.
5. Consult the datasheet for the 40106
provided and find the stated values for the trigger threshold voltages (for
25°C) – are your measured values within range?
6. Once VT+ and VT- have been measured, you will be able to calculate the
charging and discharging time of the capacitor using the method outlined in
the background section above, and determine the frequency of oscillation.
How does this compare with the actual measured value on CH2?
7. Screenshot the oscilloscope screens and upload this to the folder.


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Circuit 2: Monostable


1. Build the circuit as shown. (Note activate the 5V supply of scopy ON, only
when you have built and checked your circuit build. Similarly, turn Off the 5V
supply when carrying out amendments to your circuit build). In your Kits, you
will use one of the momentary push button switches. The momentary switch in
your kit has two separate switches which both operate on the action of the
push button. You only require one of the switches. To identify the operation of
each push button switch, the input and output tags of the switch are on
opposite sides of the casing. To place into your circuit, connect one side of
the push button switch to the 22k resistor and pin2 of the 4011 nand Gate.
Connect the opposite side of the switch to the 0V rail. You may test the
operation of the switch by quickly depressing the push button and viewing the
input to pin 2 of the 4011 on the oscilloscope. (See note 6 below for setting up
the scope channels and triggering) You will see a pulse of the order 200ms
going from high +5v to low 0V, returning high again to +5V
2. Note that both the 4011 and the 74LS00 are present as multi-unit symbols.
All the U17 units belong to a single CD4011 IC, and both U19 units below to a
single 74LS00 IC. As always, focus on the pin numbers.
3. Note also that the inputs of the “leftover” NAND gate in the quad 4011
(schematic symbol U17D above on the left hand side of the schematic) are
pulled HIGH; this is required for stability. There should be no need to pull
HIGH the inputs of the leftover 74LS00 NAND gates.
4. Note that CH1 is monitoring the input of the monostable (pin 2 of the CD4011
IC) while CH2 is monitoring the output of the third NAND gate (pin10 of the
CD4011 IC)
5. Set oscilloscope channels 1 & 2 time base to 200ms/div, amplitude 1V/div.
Software ac coupling off. Select Trigger bottom RHS of screen, Trigger mode
Normal, channel 1 condition rising edge.. On channel 1, select single , Run ,
(the screen will indicate waiting), momentarily press the push button switch
on/off to trigger the monostable.. Once input pulse & output pulse displayed
press stop. Screenshot and upload. Also shoot a video of the build and the
SCOPY screen and upload.
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6. Now move the oscilloscope probes so that;
Ch1 now monitors pin 3 of the 4011 nand gate
Ch2 -- ---- “ ------pins 5&6 ---- - -“------------“------
Once again use the oscilloscope one shot facility, as explained in note 6
above. Capture the waveforms, screenshot and upload. Fully explain in your
notebook the generation & timing of these two waveforms, starting with the
activating of the push button switch.
7. As t = RC log (V /V) a monostable made from a CMOS gate with a
switching point of V would give a pulse width of RC log (5/V). According to
the specifications for this gate a typical switching point would be within the
range of 2.25 to 2.75 Volts. Bearing this in mind, calculate the shortest and
longest pulse width you would typically expect from this circuit. What is the
pulse width of your circuit in relation to these typical values? Check that
triggering the push button switch at any time after the monostable has been
activated does not affect the length of the output pulse.

You have now designed, built and tested two sampling pulse circuits using logic
gates.


END of TIMING LAB
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