CSEE - University of Essex
CE869 - Assignment 1: Settable countdown timer
with 4-digit 7-segment display
Set by: Dr Xiaojun Zhai ([email protected])
Distributed to students: week 16
Submission deadline: see FASer
Feedback: three weeks from submission deadline
Submission mode: electronic only via FASer
Assignment objectives
This document specifies the first of two coursework assignments to be submitted by students taking
CE869. This assignment is relatively simple, and is designed to give learners a first experience of
using VHDL, the Xilinx Vivado software suite, and the Basys3 design board.
You will be expected to learn to: a) implement a digital design in VHDL code; b) synthesise and
simulate your design; c) debug and verify that the design meets the specifications; d) demonstrate
about your design.
You will be given template VHDL code that will run on the target hardware (a Digilent Basys3
board with a Xilinx FPGA) and/or using VHDL simulator. You are required to add to this code in
order to implement a design that meets the specifications (below). There are many ways of coding
this design, and you are required to submit working and correct code, as well as a discussion of
alternative codings. In this first assignment, in order to encourage a modular coding style (allowing
for greater flexibility, maintainability, modularity, and reusability), you are asked to implement and
submit several partial nested designs with increasing level of functionality (see below).
You are supposed to gain familiarity with VHDL coding during the supporting CE869 lectures
and through self-study hours, also with the help of the recommended textbook or any other book
about VHDL. You are expected to work on this assignment mostly during lab hours. Your design
project should be stored under the revision control repository that was assigned to you at the
beginning of the course. You are supposed to commit often and describe your progress in the commit
messages. You are encouraged to use the Moodle forum and engage in constructive discussions with
your fellow classmates and with the module supervisor about questions, possible solutions, and
problems you may encounter while working on this assignment (please follow the forum’s rules
on the Moodle page). In order to promote a learning scheme that values the learning process in
addition to the submitted final design, your weekly progress (as traced back by the commit logs)
and your active participation to the forum will contribute to your assignment mark.
Design specifications
Your final task is to implement a settable countdown timer showing the remaining time on the
4-digit 7-segment display of the Basys3 board. The timer has two modes of operation: “SET”
and “GO”. The central button on the board toggles between the two. In “SET” mode, the user
is allowed to set the initial time in minutes (the seconds will always be 00). The up and down
buttons can be used to increment or decrement the minutes in a range from 0 to 60. If the current
value of the seconds is different from zero, pushing the up button moves to the next integer number
of minutes (rounds up) while pushing the down button moves to the previous integer number of
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Figure 1: Hierarchy of the design project. Files marked by a purple dot are provided, while files
marked in green should be implemented by the student in order to achieve the desired functionality.
minutes (rounds down). In “GO” mode, the timer should count down from the current value towards
zero at a rate of approximately 1 second.
For example, assuming the timer is counting down and currently showing 12.07, the user can set
the initial time to 14 minutes by: a) pushing the central button to enter “SET” mode; b) pushing
the top button to show 13.00 c) pushing the top button to show 14.00 d) pushing the central button
to start the counting. The display should then show the sequence 13.59, 13.58, . . . , 00.01, 00.00.
Switching to “SET” mode should not automatically set the number of seconds to zero (resetting
takes place only when up/down is pressed) so that the central button can be used to pause and
resume the counting.
In order to encourage a modular coding style, you are asked to implement and submit several
partial nested designs with increasing level of functionality:
1) 7-segment decoder: the user should be able to use the rightmost four switches, SW3–SW0, to
input a BCD (0–9) digit that is then displayed (duplicated) on all four digits of the Basys3
display;
2) manually-multiplexed 4-digit 7-segment decoder: the user should be able to use the sixteen
switches, SW15–SW0, to input four BCD (0–9) digits that are then displayed, in turn, on
each one of the four digits of the Basys3 display; the user manually simulates the multiplexing
clock by pressing the central button;
3) settable countdown timer with 4-digit 7-segment display: complete final design as described at
the beginning of this section.
Each student is given access to a personal repository containing a Xilinx Vivado project and
some VHDL code. Figure 1 shows the hierarchy of the project and the files provided.
In particular, the file main0 dummy.vhd provided, when set as “Top Module”, can be synthesized
into a test design that you should use to familiarize with the pinout and the polarity of the Basys3
7-segment display (which is wired for time-multiplexing).
Your first task is to set main1 one digit.vhd as the top module and then create a new file,
one digit.vhd, implementing the one digit entity that produces the control signals for the 7-
segment display. You should then synthesize the design in order to debug it, correct errors, and
verify that it correctly implements the design 1 above.
Then, you should set main2 four digits as the top module and create a four digits.vhd file
in order to implement the design 2 above. In this phase, you should reuse the one digit entity
that you coded for design 1. Again, you should synthesize your design and verify that it correctly
implements the specifications of design 2 above.
Finally, you should create a new top entity main3 final, and then implement the complete final
design as described at the beginning of this section. Your code should reuse the one digit and
four digits entities (see hierarchy in Figure 1).
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Suggested material
1. In order to familiarize with the Xilinx Vivado design suite you can use the software docu-
mentation or search online. If you do not find an answer to your question, you can start a
discussion in the Moodle forum.
2. Datasheets and schematics of the Digilent target board are available from the manufacturer’s
website. You will need to read sections of these documents to understand how the target
board works.
3. You will need to learn about VHDL. This will be covered in the supporting CE869 lectures.
The handout of the introductory lecture lists the suggested course textbooks as well as links
to free tutorials and other online material.
4. You will need to understand binary-coded decimal and the workings of time-multiplexed 7-
segment displays. These are topics that are explained in multiple sources, including the
Wikipedia, and many digital electronics textbooks. You should read about these topics and
reference appropriate sources in your submission.
5. It is assumed that you are familiar (from Year 1 or otherwise) with the concepts of combina-
tional and sequential digital logic, and with computer programming in a high-level language.
Important: material and sources used during your design should be appropriately referenced in the
final report; failure to make appropriate acknowledgement constitutes plagiarism and a breach of
intellectual property rights.
Submission
Your work must be submitted to the university’s online FASer submission system at the address
https://faser.essex.ac.uk/ by the deadline given on the system. No other mode of submission is
acceptable. You are strongly advised to upload a draft submission before the last lab hours prior
to the deadline, and then update it up to the deadline. You are required to submit one ZIP archive
containing the following files:
1. The file one digit.vhd implementing the one digit entity;
2. The file four digits.vhd implementing the four digits entity;
3. The file main3 final.vhd and all the additional files it depends upon;
4. Your repository log in .TXT format (detailed instructions on how to export it from GIT, will
be given through the forum);
5. If you want (in your own interest, see marking criteria), add an appendix to the report with
the transcripts of relevant forum discussions you contributed to.
DO NOT WAIT UNTIL CLOSE TO THE DEADLINE TO MAKE YOUR FIRST SUBMIS-
SION. Difficulties with the submission system will not be accepted as an excuse for a missing
submission.
Marking criteria
This assignment is worth 20% of the module mark. Marks will be awarded for the VHDL code,
including coding style and quality. In addition to the submission, each student will be expected to
demonstrate and explain her/his design with confidence and competence during a demo lab session.
Marks will be assessed based on:
• Implementation
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– Quality of the implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40%
– Modular design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20%
– Generic and re-usable code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15%
– Proper use of comments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10%
– Steady progress, adequate use of GIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10%
• Others
– Compliance with submission instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5%
Marks below 100% can earn additional credits if the student actively engaged in forum discus-
sions asking pertinent questions and giving competent answers to questions raised by classmates.
Late Submission and Plagiarism
Please refer to the Students’ Handbook for details of the Departmental policy regarding submission
and University regulations regarding plagiarism.
Revision 1.0
18/11/2020
Xiaojun Zhai
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