1 | P a g e EE 476 / 576 Final Exam Due: 12/18/2020 at 12:00 PM UPLOAD TO BLACKBOARD Name: _______________________________________ Student ID: __________________________________ 1) For each problem, please state your assumptions, show all your work, and write legibly. There will be points deduction for lack of clarity. 2) You can use your notes, calculator and book. 3) 476 - please attempt Problem 3 as the choice question. 576 will attempt Problem 5. Problems 1, 2 and 4 are common to all. Process parameters (if not specified): NMOS: T0 = 0.35,′ = 200 2 , = 0.512, 2 = 0.7, = 0.25 / = 1 PMOS: T0 = −0.3,′ = 65 2 , = 0.412, 2 = 0.7, = 0.35 / = 1 Cox(PMOS/NMOS) = 5fF/um2 # 476 576 Score P1 25 25 P2 25 25 P3 25 - P4 25 25 P5 25 TOTAL - 100 pts 2 | P a g e 1. (476/576) (25 pts) In the circuit below, assume that the reference current is decreased by a factor K. Determine if the following parameters increase, decrease or stay the same as a function of K. For example, the total power consumption would scale as follows. Power dissipation decreases as P KP. Show your steps clearly. a) Small-signal low-frequency differential voltage gain, Adm (7.5 pts) b) Output Swing or Output Linear range: (5 pts) 3 | P a g e c) Input common-mode Range: (5 pts) d) Unity-gain phase margin: (7.5 pts) 4 | P a g e 2. (476/576) (25 pts) a) Find the small-signal differential mode-gain for the adjoining circuit (10 pts). b) Identify the pole locations at nodes X and Y (5 pts). c) If Cx = 0.5pF, what is the maximum tolerable value of CY that yields a phase margin of 60°. Consider (W/L)1-4 = 50/0.5, and Iss = I1 = 0.5mA (10 pts). 5 | P a g e 6 | P a g e 3. (476 only)(25 points) In the adjoining figure, assume a power budget of 3mW, required output swing of 1.8V, and effective length Leff = 0.25um for all devices. a) Assume M5 and M6 carry 0.5mA current with equal overdrive voltages, determine (W/L)5 and (W/L)6. (10 pts) b) Calculate small-signal gain of output stage (5 pts). c) Now consider the remaining 0.5mA flows through M7. Determine the sizes of M3 and M4 such that VGS3=VGS5. (5 pts) d) Finally, find the sizes of M1 and M2 such that the overall voltage gain of the opamp is >100. (5 pts) 7 | P a g e 4. (476/576) (25 pts) a) Find an expression for low-frequency small-signal gain of the common-source amplifier as shown below (10 pts). Assume gm1=gm2=gm3=gm, gds1=gds2=gds3=gds. Before you carry out the detailed analysis, write a couple of sentences describing your intuition about the behavior of the circuit (5pts). Note: neglect back-gate effects. b) Now identify the poles/zeros of this circuit at drain of M1 and drain of M2 (5 pts). c) Sketch the bode plot showing clearly the pole and zeros of this circuit (5 pts). 8 | P a g e 9 | P a g e 5. (576 only) In the circuit below, consider all transistors to be 75/0.5 except for M5 and M6 which are equal to 80/0.5. Also consider Iss = 0.2mA and each output branch is biased at 1mA. a) Determine the common mode voltages at node X and Y (5 pts) b) If each output is loaded by a 1-pF capacitor, compensate the op-amp using Miller compensation for a phase margin of 50° in unity-gain feedback. (5 pts) c) Calculate the pole and zero locations. (5 pts) d) Estimate the series resistance that will be placed to cancel the non-dominant pole. (5 pts) e) Determine the slew rate of the amplifier. (5 pts) 10 | P a g e
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