ACS11001 Digital and Embedded Systems

Assignment 2020-21

Assignment weighting

25%

Assignment released

13 November 2020

Assignment Due

23.59, Friday, 18 December 2020. You must submit the completed assignment to the ACS11001

Blackboard page as a single PDF document (use the Assignment link in the Assessment folder). You

must include your registration number (ONLY) on the title page.

Feedback

Detailed mark sheets and written feedback will be provided to each student no later than 15 January

2021. Note that marks are provisional and may be subject to change, for example, as a result of unfair

means.

Unfair Means

This is an individual assignment. The use of unfair means, e.g. plagiarism and collusion, is strictly

forbidden. Students are warned that the piece of work affected may be given a grade of zero, which

in some cases will entail failure of the module. Electronic software (e.g. Turnitin) may be used to check

for unfair means.

You should thoroughly read and understand the information at

https://www.sheffield.ac.uk/ssid/unfair-means/index, including the University’s guidance to students

on unfair means download. If you are at all unsure about what this means and the implications for

your work, then you should consult the module leader.

Extenuating Circumstances

Applications for extensions to the submission date must be made directly to the module leader via

email. This email must contain the reason for the requested extension. Before an extension is formally

granted a completed extenuating circumstances form (available from the SSID pages of the university

website - http://www.sheffield.ac.uk/ssid/forms/circs) must be submitted.

Please note that extensions will only be granted if a student cannot reasonably submit the assignment

within the original deadline and can provide a valid reason supported by appropriate evidence.

Typically extensions will only be granted in the event of medical and/or personal circumstances

beyond the control of the student and requests for extensions should be made as early as is feasibly

possible. Failure to have backed-up your data and poor planning so that everything is being done at

the last minute are not valid reasons. The decision of the module leader will be final in all requests

for extensions.

2

Assignment Questions (total of 7 questions)

For all questions on circuit design, you may assume the use of positive logic; a logic ‘1’ denotes

a HIGH or TRUE value and a logic ‘0’ denotes a LOW or FALSE value. For any logic circuit,

assume that complements of input variables are not available hence a NOT gate is needed to

provide the complement of a variable.

Question 1

Consider the boolean function F(A,B,C,D) with the expressions below. Convert each expression to the

canonical product-of-sum form.

a) (A+C)(C+D)

b) ( + )(̅ + �)

Question 2

Simplify the following Boolean expression F = AB + ABCD + ABCDE + ABCDEF as much as possible using

algebra rules. State which rule you used for each step of working. Then, verify your simplified

expression using the Karnaugh map approach.

Question 3

Simplify the Boolean function (,,,,) = Σ(1,3,7,8,9,12,20,22) with don’t care conditions

(,,,,) = Σ(0,2,10,11,14,24) and design a combinational circuit that implements the desired

operation using:

a) NAND gates

b) NOR gates

with the minimum number of cables (connections).

Question 4

Implement a combinational circuit with two outputs 1(,,,) = Π(2,3,4,6,10,11,12,13) and

2(,,,) = Σ(0,3,4,5,7, 12,13) using

a) 3x8 decoders and OR gates

b) 8x1 multiplexers

Question 5

Consider two 4-bit signed magnitude numbers A and B. The most significant bit is the sign bit and the

remainder bits represent the magnitude of the number. Design a combinational circuit to determine

if A

**B.**

3

Question 6

Given full-adders, half-adders and any logic gates where all have the number of inputs necessary,

design a 3-bit by 3-bit multiplier combinational circuit. Hence, for the multiplication of decimal

numbers 5 and 7, show the binary value on every line of input and output of your designed circuit.

Question 7

You are to design a basic home security system. Your combinational circuit has twelve inputs and one

main output to trigger an alarm. The inputs provide the state of sensors attached to windows, doors,

motion detector etc. You can use logic gates, encoders, decoders, multiplexers or anything learnt in

the module. However, the lower level your circuit is, the better it will be. This means that a circuit with

just multiplexers should receive a lower mark than one that shows implementation using logic gates.

Additionally, you will incorporate a seven-segment display that is widely used in electronic devices

such as digital clocks, electronic meters and other devices that display numerical information. The

controller for the display uses a HEX-to-7-segment decoder to display the decimal number 1 to 12 to

indicate the sensor that is activated. The input is WXYZ where W is the most significant bit. Use

Karnaugh maps to simplify the 7 logic expressions for the outputs a, b, c, d, e, f, g.

The Hexadecimal numbers (1 to C) will be displayed as follows:

HE

X-

to

-7

-s

eg

m

en

t

de

co

de

r

led display

Provide a brief explanation on how your design works. Your solution should show the complete layout

of the combinational circuit. It should be clear how the inputs are connected to other parts of the

circuit, through to the output, to trigger the alarm and set the display. For the display, provide the

simplified expressions for all 7 outputs and design the logic circuit only for the Boolean expressions

for a, c and e using only NAND gates.

W

X

Y

Z

4

Submission Format

The assignment should be submitted as a single PDF document. There is no page/word limit or

particular requirements for font types, size, page margins and line spacing. However, it is suggested

that you use either Times New Roman or Calibri and 11 point type with at least 2cm margins at the

top and bottom of the page and 1.5 line spacing.

All tables, Karnaugh maps and procedure diagrams (e.g. that represent algebraic calculations) must

be professionally produced, not hand drawn. Only the figures that represent circuit design are allowed

to be hand drawn and inserted as pictures; however, you are strongly advised to produce all figures

professionally as well, since they will result in mark reductions if the circuit is not clear (e.g. clear

cables/connections, clear gate drawings).

Help

This document should provide all the information that is required to complete this assignment. It is

not expected that you should need to ask further questions. However, if you feel that any part of this

document is not clear, you may ask/email me. Remember that you need to clearly present the

procedure that you followed to solve every question of the assignment. This is part of what you are

being assessed on besides your knowledge and understanding of the module and problem solving

skills.

Marking Criteria

See attached marking criteria – this is the mark sheet that will be used to assess the assignment. The

mark sheet indicates the marks available for each part of the assignment and some of the factors that

will be used in assessing the assignment.

Penalties for Late Submission

Late submissions will incur the usual penalties of a 5% reduction in the mark for every working day (or

part thereof) that the assignment is late and a mark of zero for submission more than 5 working days

late. For more information see http://www.shef.ac.uk/ssid/exams/policies.

欢迎咨询51作业君

3

Question 6

Given full-adders, half-adders and any logic gates where all have the number of inputs necessary,

design a 3-bit by 3-bit multiplier combinational circuit. Hence, for the multiplication of decimal

numbers 5 and 7, show the binary value on every line of input and output of your designed circuit.

Question 7

You are to design a basic home security system. Your combinational circuit has twelve inputs and one

main output to trigger an alarm. The inputs provide the state of sensors attached to windows, doors,

motion detector etc. You can use logic gates, encoders, decoders, multiplexers or anything learnt in

the module. However, the lower level your circuit is, the better it will be. This means that a circuit with

just multiplexers should receive a lower mark than one that shows implementation using logic gates.

Additionally, you will incorporate a seven-segment display that is widely used in electronic devices

such as digital clocks, electronic meters and other devices that display numerical information. The

controller for the display uses a HEX-to-7-segment decoder to display the decimal number 1 to 12 to

indicate the sensor that is activated. The input is WXYZ where W is the most significant bit. Use

Karnaugh maps to simplify the 7 logic expressions for the outputs a, b, c, d, e, f, g.

The Hexadecimal numbers (1 to C) will be displayed as follows:

HE

X-

to

-7

-s

eg

m

en

t

de

co

de

r

led display

Provide a brief explanation on how your design works. Your solution should show the complete layout

of the combinational circuit. It should be clear how the inputs are connected to other parts of the

circuit, through to the output, to trigger the alarm and set the display. For the display, provide the

simplified expressions for all 7 outputs and design the logic circuit only for the Boolean expressions

for a, c and e using only NAND gates.

W

X

Y

Z

4

Submission Format

The assignment should be submitted as a single PDF document. There is no page/word limit or

particular requirements for font types, size, page margins and line spacing. However, it is suggested

that you use either Times New Roman or Calibri and 11 point type with at least 2cm margins at the

top and bottom of the page and 1.5 line spacing.

All tables, Karnaugh maps and procedure diagrams (e.g. that represent algebraic calculations) must

be professionally produced, not hand drawn. Only the figures that represent circuit design are allowed

to be hand drawn and inserted as pictures; however, you are strongly advised to produce all figures

professionally as well, since they will result in mark reductions if the circuit is not clear (e.g. clear

cables/connections, clear gate drawings).

Help

This document should provide all the information that is required to complete this assignment. It is

not expected that you should need to ask further questions. However, if you feel that any part of this

document is not clear, you may ask/email me. Remember that you need to clearly present the

procedure that you followed to solve every question of the assignment. This is part of what you are

being assessed on besides your knowledge and understanding of the module and problem solving

skills.

Marking Criteria

See attached marking criteria – this is the mark sheet that will be used to assess the assignment. The

mark sheet indicates the marks available for each part of the assignment and some of the factors that

will be used in assessing the assignment.

Penalties for Late Submission

Late submissions will incur the usual penalties of a 5% reduction in the mark for every working day (or

part thereof) that the assignment is late and a mark of zero for submission more than 5 working days

late. For more information see http://www.shef.ac.uk/ssid/exams/policies.

欢迎咨询51作业君