辅导案例-ECE 341-Assignment 3

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ECE 341
Fall 2020
VHDL Programming Assignment 3
Due: October 7 at 11:59pm
The following are the objectives for this assignment:
• Expand the gate library from Programming Assignment 2 to include flip-flop models and
gates that have wider fan-in
• Develop behavioral, dataflow, and structural models for a simple sequence detector
• Learn about testbenches and to develop a testbench to test the sequencer model.
1. (10) Expand your gate_lib library from VHDL Programming Assignment 2 to include models for
D, SR, T, and JK flip-flops. The flip-flops should include active low asynchronous reset and
clear signals. Model your flip-flop models using processes without sensitivity lists.1 All flip-
flops should include asynchronous preset and clear signals. Note that each flip-flop should
have its own entity and architecture. Assume the propagation delay for the flip-flops (clock
edge to output change) is 200 ps. Furthermore, add 3&4 input models to your library for the
following logic gates: AND, OR, NAND, & NOR. These gates should also have a
propagation delay of 100 ps+(2−#inputs)×10 ps .
2. (10) Using the state diagram for the sequencer described in Homework 1 (2019 edition) problem
10, create a behavioral simulation model (see Fig. 2-54 or 2-56 for examples) for the
sequencer. Augment your model by adding an asynchronous reset input signal.
3. (10) Create a test bench that tests the model for correct operation. Use your test bench to verify
the operation of the sequencer.
4. (10) Using the same entity created in Part 2, create a logic equation or "dataflow" model for the
sequencer (for example, similar to Fig. 2-57). Your test bench should be identical to the test
bench created in Part 3.
5. (10) Again, using the same entity for the model in Part 2, create and verify a gate level model for
the sequencer using T flip-flops. Again, your test bench should be identical to the test bench
created in Part 3.
For each part, provide a brief write-up that summarizes your design process, and testing strategy.
Include any information not already provided in your homework solution.
Your workspace should be organized into two designs: gate_lib, and detector.
For this assignment, name your workspace according to the rules described in the first assignment
(yourname_vhdl3). As with the previous assignments, submit your assignment using the following
Dropbox upload link:
https://www.dropbox.com/request/vP2leS2AB1Rf6Dw6UTF2
Note that this assignment includes supplemental material on 1) what a test bench is and how to use
it, and 2) how to rerun Aldec simulations (for a live demo, see the Sep 23 lecture).
1 See Introduction to VHDL part 2 of 5, slide 23 for a simple example.
The VHDL Test Bench
The purpose of a test bench is a to test your model. The test bench model is a virtual model for your lab bench. In the
lab, if you were to wire up and test a circuit, you will need connect your inputs to either a function generator or switches
and then use an oscilloscope or logic analyzer to capture the circuit outputs. The test bench provides these capabilities
To the point, a VHDL test bench is a VHDL model whose entity has no signal inputs or outputs. In the test bench
architecture, any inputs and outputs required to hook up your model are declared as signals in the test bench. The
model you are testing is instantiated in your test bench. Finally, the inputs and any changes to the inputs are VHDL
code you write to match your desired testing. For example, the following test bench would be suitable for testing a two-
input NAND gate:
library ieee;
use ieee.std_logic_1164.all;
-- the test bench entity. Not there are no signal inputs or outputs
entity testbench is
end entity testbench;
architecture test of testbench is
component NAND2 port(I0,I1:in std_logic;F:out std_logic);
end component;
-- declare the signals that will serve as the inputs and outputs for the NAND gate
signal I0, I1, F:std_logic;
begin
-- instantiate the NAND gate
UUT: NAND2 port map(I0,I1,F);
-- input stimulus that will apply all input combinations to the NAND gate
I0<='0','1' after 10 ns, '0' after 20 ns, '1' after 30 ns;
I1<='0','1' after 20 ns, '0' after 40 ns;
end architecture;
Aldec has a tool that generates an empty test bench for your model. The code generated provides all the basic
declarations and leaves comments directing you where you can include your code.
For clocked sequential machines, the test bench is used to generate the clock. The following process creates a 1GHz
clock:
clockProcess1: process -- process to generate a 1GHz clock
begin
clk<='0'; wait for 500 ps;
clk<='1'; wait for 500 ps;
end process;
You can also create a process that generates both circuit inputs and the clock:
clockProcess2: process
begin
X <= '0';
clk<='0'; wait for 500 ps; clk<='1'; wait for 500 ps;
X <= '1';
clk<='0'; wait for 500 ps; clk<='1'; wait for 500 ps;
-- . . .
end process;
You can also do interesting things with loops:
clockProcess3: process
constant inputs:std_logic_vector(0 to 9):="01010101";
begin
for i in 0 to 9 loop
X <= inputs(i);
clk<='0'; wait for 500 ps; clk<='1'; wait for 500 ps;
end loop;
wait; -- permanently terminates the process
end process;
Throughout the semester we will be using test benches and more complex & capable test benches will be presented.
Rerunning an Aldec Simulation
As discussed in class, rerunning Aldec simulations after exiting and returning to Aldec is quirky.
Aldec simulation results are stored in a special database file with an asdb extension. This file
contains all of the details of your simulation. The second file, with an awc extension, references the
database file and allows the user to create the perspective (signal ordering, appearance, etc.) that
best helps to understand your results. Many of you have tried to rerun simulations only to find
either your stimulus is lost or you cannot change the waveform displayed. It turns out that Aldec
allows you do do these things, but the steps to accomplish this are not obvious.
If you have a simulation from a previous session and want to rerun the simulation with the same
starting conditions, such as with the stimulators you previously created, please use the following
procedure:
1. When you run your simulation the first time, be sure to save the waveform. When you save
the waveform, two files should appear in the design, one with an asdb extension and the
other with an awc extension. Exit Aldec
2. Open Aldec.
a. If you simply want review simulation results from a prior session, open the file with the
awc extension. Your previous simulation results should be displayed.
b. If you want to run a new simulation using the original starting point from the previous
session, open the asdb file instead. You should also be able to see your simulations
results. The file opened in the new tab will be named "untitled.awc"
3. Continuing from 2.b., if you want to run a new simulation, choose the Structure tab in the
Design Browser and make sure the model you are interested in is displayed in the top line of
the window.
4. Under the Simulation menu, choose "Initialize Simulation". Be aware that there is no visible
change in the waveform at this time
5. Under the Waveform menu, choose "Connect to->Simulation". Note that now, the
waveforms have been cleared and your stimulators are still present.
6. Run your simulation as desired. You are free to modify the signals that are in the waveform,
their appearance, and their order.
7. When you are done, save your simulation results as you had done in the prior session.

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