EE380 Fundamentals of Electronic Circuits
Fall 2020
Homework #6
Due Mon Oct 5 at 2:20PM

Please write clearly and draw a box around all answers. You will not get credit if your work
is difficult to follow or the answer in a box is not easily seen. Numerical values must
generally have 3 significant figures and units. Include an annotated schematic for all
problems that include circuit analysis or design. You will receive credit for the work shown.

Use these parameters. For any other parameters, use the transistor parameters in the
tsmc018.mod.txt file.

VDD = 1.8 V
 = 0.09 m
n = 0.580 V0.5
p = -0.576 V0.5
kn' = 223 A/V2
kp' = 94.3 A/V2
|F| = 0.3 V for
both transistors
VAn' = 15 V/m
VAp' = 10 V/m

1. Calculate the resistance (RD or RL), VGS, VO, VDC, voltage gain (as a ratio and in dB),
input resistance and output resistance for each of the four amplifiers shown in the
schematic (on page 2) using the following parameters. RS = 6.0 k. The transistors are
sized at 80/6 with  = 0.09 m for the TSMC 0.18 m process. The body terminals are
connected to ground. The bias current is 15 A. For the DC bias calculation, ignore
channel length modulation for all cases and ignore the body bias effect except for the
common-drain amplifier. In that case, you will need to iterate to find the threshold
voltage since, threshold voltage depends on body bias and the body bias depends on
threshold voltage. This part of the problem annoyed me, so I gave you the answers in
the chart. You don’t have to calculate these numbers for yourself. VBIAS = 0.6 V. Fill in
the following table with your values. The signal source is vsig. The Rsig = 100  resistor
represents the series resistance of an actual signal source. Calculate Vo for maximum
signal swing.
Parameter Common-Source CS w/RS Common-Gate Common-Drain
RD or RL, k
VGS, V 0.653V
VO, V 0.574V
VDC, V
Avo, V/V
Avo, dB
Rin, k
Ro, k


2. Using the results from the previous problem, sketch the total input voltage and total
output voltage for each amplifier if vsig = 10 sin(t) mV. Use the same scale for each
plot and plot two complete cycles. The frequency of the small-signal input is 10 MHz.
(Use Matlab or another tool to make the sketches non-sloppy)


























VDD
cs
Rsig
RD
vsig
VDC
VDD
csrs
Rsig
RD
vsig
RSVDC
VDD
cd
Rsig
vsig
RL
VDC
VDD
cg
Rsig
RD
vsig
VBIAS
VDC

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