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University of Wollongong
School of Electrical, Computer and Telecommunications Engineering
ECTE432/832 Computer Architecture 2020

Laboratory Project


Laboratory activities and project are worth 30% of the overall grade for ECTE432/ECTE832 subjects
(10% for the project report, 5% for the final demonstration and 15% for weeks 3-13 Laboratory
participation and performance). The purpose of the laboratory project is for students to obtain a
deeper understanding of the MIPS architecture as well as pipelining techniques.

Students are required to create and submit a Matlab Simulink model that implements a Single
Cycle MIPS datapath, and extend it to a pipelined Multi-Cycle datapath with subroutine
capabilities. A maximum four-page of their design and implementation and the simulation codes
should submitted by 11:00 am Friday week 13. The submission is through the e-learning site.

Students will implement a single cycle MIPS datapath as discussed in lectures and then extend it to
include subroutine and pipelining capabilities (multi-cycle). Students may use the components
generated in Laboratory 1 towards their design (with some modifications), or they may choose to
create their own components from scratch using any of the blocks available in Simulink. This includes
anything from designing with basic blocks, to using VHDL/Verilog black boxes. Students must ensure
that their model works with the Simulink environment provided in the school laboratories. This means
students using different version of Matlab/Simulink/Xilinx tools MUST ensure compatibility with the
laboratory setup. Students must also ensure that there are enough visible components so that the
marker can verify the correctness of their design.

Project Details

The basic requirements for this project are as follows:

1) To design and simulate a simple single-cycle MIPS datapath found in the textbook 3rd/4th /5th
editions. (see attached Figure at the end of project details)

All datapath components will be needed, including the control unit and ALU control block which
provide the rest of the datapath with control signals. The datapath must be able to implement at
least the following instructions:
R-type instructions: add, sub, and, or
I-type instructions: lw, sw, beq, addi, lui, slti
Control flow: bnq, beq, j
Students will be asked to simulate the following short program:
## Program for ECTE432/932 Project Laboratory .text
2
.globl main
main:
addi $t0, $zero, 3 # store 3 as our first number

addi $t1, $zero, 50
 # store 50 as our second number

addi $t2, $zero, 300 # store 1 in $t2

lui $t3, 0x4000
 # memory data top two bytes

sw $t2, -8 ($t3) 
# store answer to memory
loop:
 lw $t2, -8 ($t3)
 # load the current answer
sub $t2, $t2, $t0 
 # $t2=$t2-$t0
addi $t1, $t1, -1 
 # decrement second number
addi $t3, $t3, 4
 
 # next memory data location
sw $t2, -8 ($t3)
 
# store answer to memory

bnq $t1, $zero, loop # branch back to loop while $t1 is not zero
## End of program

2) To design and simulate a simple Multi-cycle MIPS datapath to include two new instructions; Call
Sub and Return. When “Call Sub” instruction is detected, the system saves the content of PC in a
memory location or in one of the registers and then jumps to the Subroutine address. When “Return”
instruction is detected, the system restores the PC with the content of memory or allocated register
and continues the program after the “Call Sub” line. You don’t need to provide for nested
subroutines. The datapath could be extended to handle the additional instructions.

All datapath components will be needed, including the control unit and ALU control block which
provide the rest of the datapath with control signals. The datapath must be able to implement at
least the following instructions:

R-type instructions: add, sub, and, or
I-type instructions: lw, sw, beq, addi, lui, slti, bnq
J-type Call Sub, Return

Students will be asked to simulate the following short program:

## Program for ECTE432/932 Project Laboratory
.text
.globl main

main:
3
addi $t0, $zero, 1 # store 1 as our first number
addi $t1, $zero, 20 # store 20 as our second number
add $t2, $zero, $zero # the answer spot is cleared
lui $t3, 0x1000 # memory data top two bytes

add $t5, $zero, $zero # loop flag
sw $t2, 0 ($t3) # store answer to memory

loop:
lw $t2, 0 ($t3) # load the current answer
and $t5, $t2, $t3 # no purpose - just a pipeline hazard
or $t5, $t2, $t3 # no purpose - just a pipeline hazard
Call Sub Subroutine
slti $t5, $t1, 1 # set the loop flag if second number < 1
beq $t5, $zero, loop # branch back to loop while flag == 0


Subroutine:

add $t2, $t2, $t0 # add first number to it
addi $t1, $t1, -1 # decrement second number
addi $t3, $t3, 4 # next memory data location
sw $t2, 0 ($t3) # store answer to memory
Return

## End of program
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Where to start?

A good place to start is the lecture notes for Lecture 2 as well as the description of the Instruction set
in Chapter 2 of the textbook. The textbook gives a thorough description of the single cycle MIPS
datapath as well as specifications for the control unit and ALUop control block. Lecture 4 notes give
further details on a pipelined version of the datapath.

Students need to design the extra hardware needed to implement “Call Sub” and “Return”
instructions. Draw a complete datapath that is capable of implementing the instruction set.

Also, entering the programme into a MIPS simulator will help students understand the changes in
various datapath components at each step of the programme. A recommended simulator is Spim,
which is available for download from http://sourceforge.net/projects/spimsimulator/files/ (older
versions available at: http://pages.cs.wisc.edu/~larus/spim.html ) or also comes on CDROM with the
textbook. The zipped windows executable format can be downloaded, unzipped and run from any
location on a windows machine. Additional material about assemblers, linkers and the SPIM
simulator can be found here: http://pages.cs.wisc.edu/~larus/HP_AppA.pdf ). Loading the assigned
program and running it in Spim will allow students to see register and memory values.

It is anticipated that students will need to spend significantly more time on this project than that of
their allocated laboratory times. Thus, it is in the students’ best interest to use the allocated
laboratory time (with demonstrator supervision) to ask questions, to clarify project requirements,
and to demonstrate their progress. The rest of the project must be completed during the students’
own study time.

Design Considerations

Students should consider how to implement each of the components in the single cycle MIPS and the
extended multi-cycle MIPS datapath, including the ALU, control unit and ALU control block. The ALU
designed in Laboratory 1 can be used as a starting block, though some modifications may be
necessary in order to execute all instructions given in the project. Students will also need to consider
their implementation of the register file and memories and should pre-enter their program into the
Instruction Memory, as well as pre-setting the Program Counter with the address of the first
instruction to execute.

In addition, the students need to consider which outputs are necessary in order to show/prove that
their design operates correctly. It is the student’s responsibility to demonstrate that their model
operates correctly. Thus, any bus values, control signals, multiplexors or internal register values that
help show the correct operation of the model must be made visible for the marker – some example
ways of showing output include: a display block as part of the model; or a list of signals to add to the
Wavescope analyser. Additionally, students must ensure their model can be stepped through in a
single-step fashion to allow the marker to progress when they are convinced the current instruction
has operated correctly.


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Project report

In order for the Projects to be marked in a timely manner, students are also required to submit a
maximum four-page report, descripting their project including the following information:

• Describe your implementation, including how you implemented each component. Describe
the challenges and the outcome. Describe where the components are situated on the screen
– so that the marker is able to quickly understand where to find everything.
• Describe which outputs you have made available and where, so the marker can find these
outputs on the screen – or which signals to add to the Wavescope analyzer. Also describe
how these outputs show that your datapath operates correctly.
• Describe the simulation parameters that should be used by the marker to effectively see the
operation of the entire program – as well as any other information the marker needs to know
to simulate your model. If your model requires initialisation, specify here the steps that need
to be taken.

• Describe your modified datapath that enables “Call Sub” and “Return” Instructions.


The report should be in a format easily read by the marker (.doc, .pdf, .txt). If any of the above points
require references to images of the model to facilitate finding components or signals, these images
can be attached to this document on additional pages, though this is not necessary. Students should
still only submit one document for this portion of the project.

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Assessment Guidelines and Marking Criteria

The scope and complexity of this project are designed to give the student as much flexibility as
possible. Students may submit models in varying degrees of completeness based on the levels of
achievement on the last page of this document. Please check these guidelines. The students will be
given a mark for their design, a mark for their model file and a mark for their report. The final mark
for their project is weighted as follows:

Report on Design and implementation and challenges 5 marks
Results and Discussion on MIPS datapath implementation 5 marks

Total for the project: 10 marks

Pre-submission checklist

Below is a pre-submission mental checklist that students should go through before submitting their
models and two-page descriptions:
• Have you checked the guidelines and marking criteria above to ensure you understand the
requirements for the level of achievement you are aiming for?
• Have you checked your model works correctly in the environment on the laboratory
computers?
• Have you pre-entered the program into the Instruction Memory and pre-entered the Program
Counter value to point to the first instruction to execute?
• Does your two-page description accurately illustrate your datapath design and extra
components needed to implement “Call Sub” and “Return” instructions?
• Does your report accurately give instructions on the operation of your simulation? (Including
simulation parameters or initialisation details)
• Do both your report and your model file/s include, somewhere, your name and student
number for clear identification of your work?
• Have you included *ALL* files including your report to your ZIPPED submission file?

Submission

• Electronic submission by Moodle eLearning site drop box with ONE ZIPPED FILE submission
named with letter "u" for ECTE432, or "p" for ECTE832, together with your student number
(i.e. "u1234567" or "p7654321"). Please use WinZip-compatible zip compression – do not use
*.rar, *.tar.gz or other compression programs. Submissions with multiple files will not be
accepted.

The project is due 11:00am on Friday week 13

Failure to submit electronic copy via submission site according to directions, or using incorrect file
name, or multiple files or submission without clear reference to student name/number will result
in LOSS OF MARKS.



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single-cycle MIPS datapath



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Assessment Guidelines for the MIPS datapath implementation
* Students wishing to achieve at High distinction must implement a fully functional pipelined version
of the extended datapath
High Distinction [85-100%]
The student has submitted a completely operational pipe-lined extended MIPS datapath as per this
Project Description, with hazard detection/resolving implemented. All instructions execute correctly
(correct data forwarded) and all datapath components have been implemented correctly. Students
at the higher end of this achievement level have resolved hazards (eg stalling), while students at the
lower end of this achievement level have implemented hazard detection only.
Distinction [75-84%]
The student has submitted an operational extended MIPS datapath as per this Project Description.
All instructions execute correctly when viewed individually and all datapath components have been
implemented correctly. The program runs well and produces the correct result at all times.

Credit [65%-74%]
The student has submitted a close-to-completely operational extended MIPS datapath as per this
Project Description. All instructions execute correctly and all datapath components have been
implemented correctly. The program runs well and produces the correct result at all times.
Pass [50%-64%]
The student has submitted an operational single-cycle MIPS datapath as per this Project
Description. At least one (or more) instructions execute correctly and all datapath components that
have been attempted, operate correctly. Students at the higher end of this achievement level have
multiple instructions executing correctly, while students at the lower end of this achievement level
may only have one instruction working.
Poor/Fail [0%-49%]
The student has submitted a non-operational or partially operational single-cycle MIPS datapath as
per this Project Description. Some parts of the datapath may operate correctly, however no whole
instructions work correctly. The student has attempted to implement a small number of datapath
elements other than those supplied in Lab1 (or no elements at all).