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ECTE433/ECTE833/ECTE933: Embedded Systems
FPGA Design Project

Due date: Thursday, 21 May 2020, 11:30AM (Week 10 of the revised UOW calendar)
Assessment weight: 35%
Total marks: 35

This project allows you to practice the FPGA design skills learnt in the lectures, laboratories and tutorials, as there
is no better and more exciting way of understanding the material than applying it to solve a practical problem. The
project has two tasks: Task 1 is compulsory for all students, whereas Task 2 is optional and attracts bonus marks.

Project Task 1: Cube Root Finder (compulsory, 20 marks)

On 10/12/2007, Alexis Lemaire set a world record by finding the 13th integer root of a 200-digit number in
only 70.2 seconds (http://en.wikipedia.org/wiki/Alexis_Lemaire). Inspired by this achievement, this project
requires you to develop a high-speed FPGA design that calculates the cube root of an integer.

• The device has two input signals: ‘x’ and ‘start’.
• Signal ‘x’ is an unsigned positive integer. The bit-width for ‘x’ is W bits, where W is a parameter
specified in the PreLoadFcn function of the Simulink MDL file. W can be set to 8, 10, 20, 32, and so on.
• Signal ‘start’ is a Boolean variable. When signal ‘start’ goes HIGH, calculation should begin. It is
assumed that signal ‘start’ will not go HIGH again until calculation is completed.
• The device has three output signals: ‘y’, ‘valid’, and ‘clock_count’.
• Output signal ‘y’ with a bit-width of W stores the cube root of ‘x’, calculated to the first binary digit. For
example, for x = 18, output ‘y’ should be equal to 2.5d because
√18య ൌ 2.6207ୢ
ൌ 10.1ୠ (round-down to one binary digit)
ൌ 2.5ୢ
• When the device finishes calculating ‘y’, it should make Boolean signal ‘valid’ go HIGH for exactly one
clock cycle.
• Output signal ‘clock_count’ should store the actual number of clock cycles used to calculate ‘y’. For each
example, if calculation starts at clock cycle 2 and finishes at clock cycle 102 (‘valid’ = HIGH), then
‘clock_count’ = 102 − 2 = 100.
• The design must be created using MATLAB Simulink and Xilinx System Generator. The following built-
in Xilinx blocks must not be used: MCode, Black Box, Natural Logarithm, Square Root.
• Xilinx ISE version 14.4, MATLAB 2012b, Windows 7 or 10 64-bit are the assumed platform.

For background information, see http://en.wikipedia.org/wiki/Cube_root.





y
clock_count
valid
x
start
FPGA
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On Moodle, there is a template file ‘Project_Template.mdl’ that contains the necessary input/output ports and
start-up parameters. While you are free to move the existing input and output blocks in the template file, do
not modify their parameters. Rename the template file to the form of ‘Project_StudentID_Surname.mdl’ and
start your work. For example, for student Jay Beta, ID 1122333, the design file should be
‘Project_1122333_Beta.mdl’.

Table 1: Testing the cube root divider.
Test Case W x Correct y Actual y?
1 9 18 2.5
2 9 30 3.0
3 16 3210 14.5
4 22 202020 58.5


Create also a text file with name ‘Project_StudentID_Surname.txt’ that stores information about your design’s
performance (clock counts and the numbers of Xilinx blocks). The file should have the following format where
the blue text is specific to your MDL design. Adhere to the strict formatting because during project marking,
this file will be first processed by a computer program.


Student = Jay Beta
Student ID = 1122333
Total clock count for Test Cases 1 to 4 = 2942
Clock count for Task 1 Test Case 1 = 277
Clock count for Task 1 Test Case 2 = 342
Clock count for Task 1 Test Case 3 = 820
Clock count for Task 1 Test Case 4 = 1503
Number of Divider Generator blocks = 2
Number of Mult blocks = 1
Number of AddSub blocks = 2
Number of Mux blocks = 1
Number of Counter blocks = 2
Number of Register blocks = 8
Number of Shift blocks = 2
Number of Reinterpret blocks = 1
Number of Relational blocks = 3
Number of Logical/Expression/Inverter blocks = 5
Number of Delay/Constant blocks = 4


Design competition
• To encourage excellent efforts by students, a design competition is organized and the top 5%, 10%, or
15% solutions for Project Task 1 will be awarded extra 5.25 marks, 3.5 marks, or 1.75 marks,
respectively. These solutions should also be at level-5 in operation, algorithm, and presentation (see
Table 2).

• The competition criterion is the processing speed. Firstly, submissions are short-listed according to the
number of clock cycles (clock_count) used to process the test cases in Table 1 (Note: Designs entirely
based on the table-lookup approach are not acceptable). Secondly, an undisclosed test case will be used
to select the competition winners.
• When two submissions have the same speed, ranking is based on the quality of presentation and the
resource usage.

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Project Task 2: FPGA Graphical Application using VHDL/Verilog (optional – 3 marks)
Develop a graphical application to be run on the Spartan-3E Starter Kit. You are free to choose which
application to implement. It should involve writing VHDL or Verilog code for the FPGA board to interact with
at least the VGA monitor and one input device. The input device can be the keyboard or the mouse. Example
applications (graphic games) are shown at:
http://documents.uow.edu.au/~phung/teach/ecte433/FPGA_tetris.avi
http://documents.uow.edu.au/~phung/teach/ecte433/FPGA_roachwars.avi

• This project task is optional. Students who are able to complete this project task will be awarded extra
3 marks.
• For this project task, study ‘Spartan-3E Starter Kit Board User Guide’ and other resources available on
Moodle. Search also the Internet for reference VHDL/Verilog code for the Spartan 3E Starter Kit.

Marking guide
The project will be marked out of 35 using the rubric shown in Table 2. This is not a group project.
Submitting work that is not your own will result in a mark of 0 and other penalties according to the
University Rules. Letting other students copy your work will result in the same penalties.


Table 2: Marking rubric for the project.
Design
Aspect
Performance Band
Level 0 (0%) Level 1 (20%) Level 2 (40%) Level 3 (60%) Level 4 (80%) Level 5 (100%)
O
pe
ra
tio
n
(1
4
m
ar
ks
)
Lacks necessary
design blocks.
Does not
execute.
Executes but
produces
significantly
incorrect outputs.
Requires some
modifications to
work.
- Works most of
the time, except
for some test
cases.
- Some output
signals are not in
the required
format.
- Works perfectly.
- Performance file
(TXT) is correctly
recorded.
- Meets all design
objectives.
A
lg
or
ith
m

(1
4
m
ar
ks
)
Algorithm is
fundamentally
flawed.
Algorithm
requires
substantial
corrections.
Algorithm is
either slow or
inefficient.
Algorithm is fast
but its
implementation
contains
extensive
redundancy.
Algorithm is fast
but its
implementation
contains some
redundancy.
- Algorithm is
highly optimized
for both speed
and resource
usage.
- Better than or
equivalent to the
sample solution.
Pr
es
en
ta
tio
n
(7
m
ar
ks
)
No visible effort
to document the
design.
Some visible
effort, but still
poor
presentation.
- Inadequate use
of comments.
- Blocks/wires are
badly arranged.
Too many
crosses.
- Some
comments are
used, but content
is superficial.
- Blocks/wires
could be
arranged better.
- Do not follow
submission
guidelines
(formatting, file
names, contents)
- Blocks are
generally laid out
with care.
- Main signals are
given meaningful
names.
- Comments
should be clearer
and more
concise.

- Concise, clear
comments are
used.
- Design is
described clearly.
- Blocks are
intelligently
organized.
- Suitable use of
sub-systems.
- Follow correctly
submission
guidelines.

Submission
• Log on to Moodle site for ECTE433, ECTE833 and ECTE933.
• Follow the links: Project  Project submission.
• For Project Task 1 (compulsory), submit two files: ‘Project_StudentID_Surname.mdl’ and
‘Project_StudentID_Surname.txt’. Use the relevant StudentID and Surname for you.
• For Project Task 2 (optional), submit file ‘Project2_StudentID_Surname.zip’ that contains ISE project file,
source code, BIT file, and readme.docx. File readme.docx briefly describes the graphical application and the
steps to test it.
Have fun designing!