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PAPER CODE NO. EXAMINER: Professor S Hall
ELEC 271 DEPARTMENT: EE&E TEL. NO: 44529

SECOND SEMESTER EXAMINATIONS 2018/19

ELECTRONIC CIRCUITS AND SYSTEMS

TIME ALLOWED: Three Hours

INSTRUCTIONS TO CANDIDATES

The numbers in the right hand margin represent an approximate guide to the marks available
for that question (or part of a question). Total marks available are 100.

Question 1 carries 40 marks. All other questions carry 20 marks.

The use of a calculator IS allowed.

Amplifier properties attached
BJT collector current is: =
where VBE is the base-emitter voltage.
= ×

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1. a) Consider the circuit of Figure Q1a. The transistor can be considered to be ideal, it
is operating in the active regime and VBE is a fixed value of about 0.6 V. If the
resistor RC is doubled in value, do you expect IC to increase, decrease or stay the
same? What would happen to IC if VCC is doubled? Explain the reasons for your

Figure Q1a

5
b) Figure Q1b shows a common-emitter amplifier circuit. Sketch the small signal
equivalent circuit for the amplifier and show that the theoretical maximum possible
voltage gain is given by 40VCC. Comment on the ideal values required for RS and RB
for the maximum gain condition.

vs
RC RB VCC RS
vo

Figure Q1b

5
IC
VBE
VCE
VCC
RC
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c) Figure Q1c shows a common emitter amplifier with emitter degradation. Calculate
the dc collector current required to produce an ac input resistance of 100 kΩ,
Take RE = 100 Ω and the ac current gain of the transistor as βo = 150.

v i
VCC
R C
v o
R E

Figure Q1c
5

Question 1 continues overleaf.
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d) For the level shifter circuit of Figure Q1d, work out a value for the voltage difference
(V1 – V2). The transistors are identical, dc current gains are large and VBE = 0.6 V.

V2
15 V
0 V
10 kΩ V1
5 kΩ
Q1 Q2
Q3

Figure Q1d

5
e) Copy the table shown in Figure Q1e into your answer script and complete it with the
words ‘infinite’ or ‘zero’, to specify the values of input and output resistance for the four
generic types of amplifier (R = resistance and G = conductance).

Voltage Current Trans-R Trans-G
Input-R

Output-R

Figure Q1e

5

Question 1 continues overleaf.

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Question 1 continued.

f) The triangular element in the circuit shown in Figure Q1f represents an ideal
current amplifier with a gain of 100. Work out the value of the voltage gain if
Rg = 1 kΩ and RL = 15 kΩ.

Figure Q1f

5
g) Draw a mid-frequency ac equivalent circuit of the amplifier shown in Figure
Q1g. (Note that bias and other components are omitted). Conduct an analysis to
find a value for the capacitor, Ci to give a low-frequency roll-off point (- 3 dB) of
100 Hz. Which circuit capacitor is usually designed to set the low-frequency roll-
off point in common-emitter amplifiers and why?
The ac current gain, βO = 100 and the circuit is biased at IC = 0.1 mA.

Figure Q1g
5
RL
Rg
+
vg
v
o

v i
Ci

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h) An operation amplifier with a slew-rate limit of 1 V/us is required to amplify a
sinusoidal 100 kHz signal. Calculate the maximum amplitude of the output
voltage that can be achieved without distortion. What type of output waveform
distortion is seen when slew rate occurs and why? (consider a 741 op-amp)
5

Total
40

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2. The figure below shows a Widlar current mirror to generate the dc current, IO.

R
R E
IO
T1
T 2
VC C
V EE

a) Neglecting base currents and assuming T1 and T2 are identical transistors, derive the
design equation for the current IO, as given by:





=
O
R
TEO I
I
nVRI l

where VT = kT/q; the symbols have their usual meanings.
6
b) The current mirror is required to provide the bias for a differential amplifier with
circuit (calculate all resistor values) to give a DC bias current (in T2 above) of
IO = 0.1 mA and DC output voltages of the differential amplifier of 0 V.
VCC = 10 V, VEE = – 10 V. Hint: allow 4VT = 100 mV across RE.
6
c) Draw the ac small-signal equivalent circuit of the amplifier and hence estimate the
differential voltage gain. Explain any approximations and assumptions used in your
calculations.
6
d) Comment on the expected magnitude of the common-mode rejection ratio. Explain
2
Total
20
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3. Figure Q3 shows an operational amplifier circuit.

Figure Q3

a) Identify the feedback topology and hence the amplification property that is
stabilised by the feedback. Derive an expression for voltage gain of the amplifier
assuming an ideal op-amp.
4
b) Sketch the equivalent circuit and hence work out a value for the loop gain, T of the
amplifier for the following op-amp parameter values:
differential input resistance, rd = 10 kΩ, output resistance, ro = 1 kΩ and
open-loop gain, Aol = 103.
10
c) Hence work out a value for the input (Rn in Figure Q3) and output resistance.
Is this a good op-amp? Explain your reasoning.
[Recall that = and =
!
"#
where Rf is the feedback resistor.]
6
Total
20

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4. a) List the advantages and disadvantages of the use of negative feedback in electronic
systems.
5
b) Draw a block diagram of an amplifier with feedback, labelling clearly the open loop
gain, Aol and feedback fraction, β. Show that the gain with feedback is given by;
A A
Af
ol
ol
=
+1 β .
Under what conditions is the closed loop gain insensitive to variations in the open
loop gain?
5
c) Figure Q4c shows an amplifier with feedback.

i) Identify the feedback topology and hence the type of amplifier. 3
ii) Represent the circuit as a negative feedback system and hence estimate the
appropriate gain, assuming that the open-loop gain of the amplifier is large
Consider the open-loop gain and use the equations given in the ‘amplifier
properties’ page to justify the assumption.
7
Total
20

Figure Q4c

VCC
5 kΩ
12 kΩ
10 kΩ
4.7 kΩ
4.7 kΩ

0
1 kΩ
0
Rf = 100 kΩ
vo
Q1 Q3
Q2
vi
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ELEC271 / Amplifier properties
Common Emitter

Common collector (Emitter follower)

Ri = rbe

Ro = RC

A v
v
g R RV o
i
m C L= = − / /

vi
Ri
RC
R
o
io
RL
v
o
( )R r Ri be o E= + +1 β Ro = RC

A
g R R
g RV
m C L
m E
= −
+
/ /
1

vi
Ri
RC
Ro
io
RL
vo
RE
( )R r R Ri be o E L= + +1 β / /

R r R Ro be S
o
E=
+
+1 β / /

A
g R R
g R RV
m E L
m E L
=
+
/ /
/ /1

( ) LEoM RRR //1 β+=
vi
Ri
Ro
io
RL
vo
RE
RS
vs

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