D. Boland 3/03/2020 ELEC2602 1
ELEC2602
Digital Systems Design
The University of Sydney
Lecture 1. Introduction to Digital Systems
3 Mar, 2020
Dr. David Boland
Lecture 1
ELEC2602
Semester 1, 2017
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Last Time…
B
A
B
A
AA•B A+B A
• Turned Boolean statements into logic gates
- Boolean operations can be represented as digital
schematics
AND OR NOT
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NAND/NOR Building blocks
NOT
A A
(A•A) = A+A = A
A
B
B
A A•B
AND
((A•B)•(A•B)) = (A•B) = A•B
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A
B
B
A A+B
OR
(A•A)•(B•B) = (A•B) = A+B
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NOR Building Blocks
A
B (A+B)
NOT
A A
(A+A) = A•A = A
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B
A A•B
AND
((A+A)+(B+B)) = (A+B) = A•B
B
A A+B
OR
(A+B)+(A+B) = (A+B) = A+B
A
B
A
B
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Constructing an XOR gate
(A•B)+(A•B)
What is the fewest number of NAND gates we need to
implement XOR?
XOR
A
B
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Constructing an XOR gate
(A•B)+(A•B)
What is the fewest number of NAND gates we need to
implement XOR?
XOR
A
B
4
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Constructing an XOR gate
(A•B)+(A•B)
We knew that this was too many:
XOR
A
B
A
A
B B
A•B
A•B
(A•B) + (A•B)
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Constructing an XOR gate
= (A•B)•(A•B)
= (A+B)•(A+B)
= A•A+A•B+A•B+B•B
= A•B+A•B
=(A•B)•(A•B)
=(A+B)•(A•B)
= A•(A•B)+B•(A•B)
DeMorgan’s
DeMorgan’s
Distributive
DeMorgan’s
Distributive
(A•B)+(A•B)
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Constructing an XOR gate
(A•B)+(A•B) = A•(A•B)+B•(A•B)
= (A•(A•B))•(B•(A•B))
DeMorgan’s
A•B
A•(A•B)
B•(A•B)
(A•(A•B))•(B•(A•B))
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Exercise
Working backwards:
Prove that the following circuit implements the
XOR function
Logician’s solution:
Write out a truth table for
Compare to XOR truth table
(A•(A•B))•(B•(A•B))
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Engineer’s solution
0011
0101
1110
1101
1011
0110
We can now check that the
output is the same as the
output of A XOR B
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VHDL: VHSIC Hardware
Description Language
• How does it fit into the design flow?
– It is NOT a programming language!
– It is an IEEE Standard method of describing hardware.
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Why do we need VHDL?
• What is wrong with schematics?
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Drawing Schematics
• Where lines cross, signifies a connection
C
R
A
B
connected
not connected
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Why do we need VHDL?
• What is wrong with schematics?
– Very easy to make mistake
– Hard to design
– How do you test it?
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How do you use VHDL?
• With VHDL, you can specify hardware in two
ways:
– Structurally: what the hardware looks like
(schematics)
– Behaviourally: what the hardware does (if…then)
• * This may not translate to hardware
• VHDL lets you combine structural and
behavioural descriptions in the same design
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Behavioural VHDL
• Describes exactly what the hardware will do using
something akin to software
• Why you might do this:
– It is easier to understand
• Eliminate any misunderstandings among designers what the
processor will do
– Make use of someone else’s optimisation
– Can simulate the design to check for mistakes
• At this stage, you have specified what the hardware will do.
This may not translate into hardware
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Combining Behavioural Units
• Divide a design into major functional units
– Write behavioural code to specify what each block does.
– Write structural code to specify how the blocks are
connected.
• Why you might do this:
– Can delegate work to individual designers (each designer will know
exactly what his/her block does)
– Can experiment with different architectural decisions (e.g. parallelism,
throughput)
– Can swap detailed designs for each module as they are completed
• Still, you have only specified what the hardware will do. This
may not translate into hardware
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Register Transfer Language (RTL)
vs HDL
• RTL specifies hardware in terms of basic building blocks
(combinational blocks, registers, etc)
– This format can be used as a source for synthesis
• Determine exactly what hardware will look like.
• Accurately estimate how fast/big your chip will be
• Why would you do this?
– You are smarter than a synthesis tool
• Check that it works!
– Simulate the design to make sure it matches behavioural code
– Simulate with descriptions of the other functional units to make sure
there are no unintended interactions
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RTL vs Gate-Level Design
• Gate level: specify design in terms of individual
gates
– Why you might do this:
• You are smarter than a synthesis tool
– This is often created automatically from the RTL
description
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A Source for Synthesis
• VHDL can be used as a source for synthesis
– A synthesis tool automatically creates an optimized gate-level
description from VHDL code
• Remember! VHDL is a hardware description language
– There are many things that we can describe, but not build
– Therefore, not all VHDL code is “synthesizable”
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Altera Quartus Prime
• Synthesis tool for this course
• Tutorial will be given at first lab, but feel free to get a head
start on your own
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VHDL Overview
library IEEE ;
use IEEE.std_logic_1164.all ;
use IEEE.std_logic_arith.all ;
ENTITY comb_logic IS
PORT ( a, b : IN std_logic_vector(2 downto 0);
p, q : IN std_logic;
x : OUT std_logic ;
y : OUT std_logic_vector(2 downto 0)
);
END;
ARCHITECTURE Behavior of comb_logic IS
Any entities (black boxes) that you want to make use of
(call them components)
Any intermediate signals
BEGIN
Simple Boolean/Arithmetic Assignments
‘Process’ statements: More complex behavioral descriptions (often ‘if’ or ‘case’)
Instantiated entities and connections
END;
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VHDL Design Entity
• A Design Entity describes a hardware block
– Basic construct for modeling a digital system in
VHDL
• Interface description (ENTITY)
• Describes the inputs and outputs of the block
• Like a function declaration
• Body (ARCHITECTURE)
• Describes what the block does, what it is composed of
• (where you specify Structural/Behavioural/RTL)
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XOR Gate in VHDL
ENTITY xor_gate IS
PORT ( A, B : IN BIT;
Z : OUT BIT);
END xor_gate;
xor_gate
A
B Z
• Declare the interface. (ENTITY)
• Only care about what the outside of the block
looks like to other hardware blocks.
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XOR Gate in VHDL
ARCHITECTURE my_defn OF xor_gate IS
BEGIN
Z <= A XOR B;
END my_defn;
A
B Z
• Define the block. (ARCHITECTURE)
• Now we describe what’s inside the entity.
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VHDL ENTITY
ENTITY xor_gate IS
PORT ( A, B : IN BIT;
Z : OUT BIT);
END xor_gate;
xor_gate
A
B Z
Ports are signals that flow
into or out of the design
Type information declares a set
of legal values for the port.
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VHDL ENTITY
• Port modes
– IN: signal can only be used as an input (can read, but cannot assign
value to it)
– OUT: signal can only be used as an output (cannot read, but can assign
value to it)
– INOUT: signal can be written to or read
– BUFFER: signal can be written to and used internally
• Types
– BIT: 0,1
– BIT_VECTOR: array of BITs
– BOOLEAN: FALSE, TRUE
– STD_LOGIC, STD_LOGIC_VECTOR
– INTEGER
– We’ll see more later…
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VHDL ARCHITECTURE
ARCHITECTURE my_defn OF xor_gate IS
BEGIN
Z <= A XOR B;
END my_defn;
A
B Z
Architecture name
An entity can have multiple architectures
Everything in the body is a concurrent statement.
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Port Modes
ENTITY bad_Model IS
PORT (A, B, C, D : IN BIT;
X, Y : OUT BIT);
END bad_Model;
ARCHITECTURE example OF bad_Model IS
BEGIN
X <= (A and B) or C;
Y <= X nand D;
END example;
ILLEGAL!
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ENTITY good_Model IS
PORT (A, B, C, D : IN BIT;
X, Y : OUT BIT);
END good_Model;
ARCHITECTURE example OF good_Model IS
SIGNAL temp : BIT;
BEGIN
temp <= (A and B) or C;
X <= temp;
Y <= temp nand D;
END example;
An internal signal fixes this problem.
Ports can also be INOUT. In that case, there are no
restrictions
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Packages and Libraries
• A package is a collection of:
– component declarations
– types, subtypes, and constants
– procedures and function declarations
• A library is a collection of packages.
• How to use packages in VHDL:
library IEEE ;
use IEEE.std_logic_1164.all ;
use IEEE.std_logic_arith.all ;
Want to use the library called IEEE.
Within the IEEE library, we want these packages
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Combinational Logic in VHDL
• We can assign a Boolean statement to any
variable
– R = (A+B)•C
– In architecture body: R <= (A or B) and C;
• Variables on the left-hand-side cannot be used on
the right-hand side:
– R = ((A+R)•(T+C))’(not allowed)
• Logic statements are concurrent
– Order does not matter
• Basic design strategy
– Each output has its own logical expression.
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Describe a block with multiple outputs
ENTITY comb_block IS
PORT ( A,B,C,D : IN BIT;
X,Y,Z : OUT BIT);
END comb_block;
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Describe a block with multiple outputs
ARCHITECTURE my_defn OF comb_block IS
BEGIN
X <= A and B and C;
Y <= C and not D;
Z <= A xor B xor D;
END my_defn;
Remember:
These statements
are concurrent!
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Design Example: Light Controller
• Two light switches in a room controlling one light:
x1 x2
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Design Example: Light Controller
• Truth table for light controller:
x1 x2 C
0 0 0
0 1 1
1 0 1
1 1 0
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Design Example: Light Controller
LIBRARY ieee;
USE ieee.std_logic_1164.all ;
ENTITY light IS
PORT ( x1, x2 : IN BIT;
f : OUT BIT);
END light ;
ARCHITECTURE LogicFunction OF light IS
BEGIN
f <= (x1 AND NOT x2) OR (NOT x1 AND x2);
END LogicFunction ;
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Internal Signals
• Alternate implementation of XOR
ENTITY xor_gate IS
PORT ( x1,x2 : IN BIT;
f : OUT BIT);
END xor_gate;
ARCHITECTURE alt_defn OF xor_gate IS
SIGNAL INT1, INT2 : BIT;
BEGIN
INT1 <= x1 AND NOT x2;
INT2 <= NOT x1 AND x2;
f <= INT1 or INT2;
END alt_defn;
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Structural Specifications
• A hardware design typically consists of composition
of smaller circuits
– This is called a structural specification
• Structural specifications can take on many forms:
– ALU (arithmetic logic unit) consists of adders/multipliers.
– Multipliers consist of many complex adders
– Complex adders consist of many ‘full adders’
– Full adders consist of many gates
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XOR Components
• Really simple example – divide XOR into blocks:
AND
AND
OR
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Creating a hierarchical design in VHDL
• Define entity and architecture for low-level blocks
• Use component declarations in architecture that
wishes to instantiate low level blocks.
– The VHDL compiler creates a "black box" when compiling
current module, connects to actual model later.
– Components can also be defined in a library.
• You can create your own libraries
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• Define each component
Structural XOR
ENTITY and_gate IS
PORT (A, B : IN BIT;
Z : OUT BIT );
END and_gate ;
ARCHITECTURE my_def OF and_gate
IS
BEGIN
Z <= A AND B;
END my_def ;
AND
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Structural XOR
ENTITY or_gate IS
PORT (A, B : IN BIT;
Z : OUT BIT );
END or_gate;
ARCHITECTURE my_def OF or_gate
IS
BEGIN
Z <= A OR B;
END my_def ;
OR
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ENTITY xor_gate IS
PORT (x1, x2 : IN BIT;
f : OUT BIT );
END xor_gate ;
u1
u2
u3
x1_
x2_
INT1
INT2
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ARCHITECTURE my_def OF or_gate IS
COMPONENT or_gate IS
PORT (A, B : IN BIT;
Z : OUT BIT );
END or_gate;
COMPONENT and_gate IS
PORT (A, B : IN BIT;
Z : OUT BIT );
END and_gate ;
SIGNAL INT1, INT2, x1_, x2_ : BIT;
BEGIN
x1_ <= NOT x1;
x2_ <= NOT x2;
u1: and_gate PORT MAP(x1, x2_, INT1);
u2: and_gate PORT MAP(x2, x1_, INT2);
u3: or_gate PORT MAP(INT1, INT2, f);
END my_def ;
u1
u2
u3
x1_
x2_
INT1
INT2
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How to implement:
out1=x1 XOR x2, out2=x1 and not x2?