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程序代写案例-6CCE3HAD

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6CCE3HAD



Department of Engineering



Hardware Design



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Assignment One











6CCE3HAD
1 Task one
Full Adder
Full Adder is the adder which adds three inputs and produces two outputs. The first two inputs
are A and B and the third input is an input carry as C-IN. The output carry is designated as C-
OUT and the normal output is designated as S which is SUM.

A full adder logic is designed in such a manner that can take eight inputs together to create a
byte-wide adder and cascade the carry bit from one adder to the another.

Figure: Full Adder
Inputs Outputs
I2 I1 I0 O1 (sum) O0 (C-out)
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
O0 I0
I1
I2
O1
6CCE3HAD
4 to 2 Encoder
An Encoder is a combinational circuit that performs the reverse operation of Decoder. It has
maximum of 2n input lines and ‘n’ output lines. It will produce a binary code equivalent to the
input, which is active High. Therefore, the encoder encodes 2n input lines with ‘n’ bits. It is optional
to represent the enable signal in encoders.
Let 4 to 2 Encoder has four inputs I3, I2, I1 & I0 and two outputs O1 & O0. The block diagram of
4 to 2 Encoder is shown in the following figure.


At any time, only one of these four inputs can be ‘1’ in order to get the respective binary code
at the output. The Truth table of 4 to 2 encoder is shown below.
Input Output
I3 I2 I1 I0 O1 O0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1

6CCE3HAD
Create a VHDL design and testbench code for the below specification? [40 Marks]


Use 4-bit input. 1-bit SEL decides to output the result of Full Adder or Encoder
Note: For the adder ignore the MSB from the input

2 Task two
8-bit Adder / Subtractor
A binary parallel adder is a digital function that produces arithmetic sum of two binary numbers
in parallel. It consists of full-adder combinational arrangement thus, the output carry from one
full adder connected to the input carry of next full- adder. In 8-bit binary parallel adder-subtractor
there are eight full adders connected in a parallel way. In this circuit the addition and subtraction
are done through the same circuit




6CCE3HAD

FA = Full Adder, all gates are XORs
When SUB = 0 the circuit works as an Adder, otherwise as a Subtractor.
4x4 Array Multiplier
The design structure of the array Multiplier is regular, it is based on the add shift algorithm
principle.
Partial product = the multiplicand * multiplier bit
where AND gates are used for the product, the summation is done using Full Adders and Half
Adders where the partial product is shifted according to their bit orders. In an n x n array
multiplier, n x n AND gates compute the partial products, and the addition of partial products
can be performed by using n x (n – 2) Full adders and n Half adders. The 4×4 array multiplier
shown has 8 inputs and 8 outputs




6CCE3HAD

Crate VHDL code using both structural and dataflow for the below design. For the input of the
4 x 4 Array Multiplier use A [3:0], B [3:0]. For the input of the adder / subtractor use A [7:0], B
[7:0].
Write the VHDL testbench to verify the results.
[60 Marks]





Opcode Operation
00 A+B
01 A-B
10 A x B
6CCE3HAD

Note: Use generate command (structural design). In the adder ignore the overflow.
Submission Instructions
1. Please submit your work on Keats
2. Provide all the VHDL files for Task -1 and Task -2. Include the screenshot of the
simulation waveform from the Modelism.
3. Create two different folders and named them Task-1 and Task-2. Copy all the relevant
files you have created for Task-1 to the Task-1 folder and Task-2 files to Task-2 to folder.
4. Create another folder and named the folder in the following way:
First name_ Surname_Student number
Once you created this folder please copy the Task-1 and Task-2 folders into this folder.
5. Right click on top of the main folder (First name_ Surname_Student number) and select
Send to after this click on Compressed



6. Once you compress the folder, please upload the folder on Keats.



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